PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 114

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
The minimum PEC response time is 3 states (6 TCL). This requires program execution
from the internal code memory, no external operand read requests and setting the
interrupt request flag during the last state of an instruction cycle. When the interrupt
request flag is set during the first state of an instruction cycle, the minimum PEC
response time under these conditions is 4 state times (8 TCL).
The PEC response time is increased by all delays of the instructions in the pipeline that
are executed before starting the data transfer (including N).
• When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, the
• When instruction N reads an operand from the internal code memory, or when N is a
• In case instruction N reads the PSW and instruction N-1 has an effect on the condition
The worst case PEC response time during internal code memory program execution
adds to 9 state times (18 TCL).
Any reference to external locations increases the PEC response time due to pipeline
related access priorities. The following conditions have to be considered:
• Instruction fetch from an external location
• Operand read from an external location
• Result write-back to an external location
Depending on where the instructions, source and destination operands are located,
there are a number of combinations. Note, however, that only access conflicts contribute
to the delay.
A few examples illustrate these delays:
The worst case interrupt response time including external accesses will occur, when
instructions N and N+1 are executed out of external memory, instructions N-1 and N
require external operand read accesses and instructions N-3, N-2 and N-1 write back
external operands. In this case the PEC response time is the time to perform 7 word bus
accesses.
When instructions N and N+1 are executed out of external memory, but all operands for
instructions N-3 through N-1 are in internal memory, then the PEC response time is the
time to perform 1 word bus access plus 2 state times.
Once a request for PEC service has been acknowledged by the CPU, the execution of
the next instruction is delayed by 2 state times plus the additional time it might take to
fetch the source operand from internal code memory or external memory and to write the
destination operand over the external bus in an external program environment.
minimum PEC response time may be extended by 1 state time for each of these
conditions.
call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum PEC response
time may additionally be extended by 2 state times during internal code memory
program execution.
flags, the PEC response time may additionally be extended by 2 state times.
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PSB 21473
Interrupts
2003-03-31
INCA-D