PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 578

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
ESP0
SETRDn
SETWRn
Enable Status Phase (for Control Transfer)
If bit ESP0 is set, the next status phase of endpoint n will automatically
be acknowledged (by an ACK or by a zero data packet, respectively)
except if the endpoint n is stalled. If ESP0 is not set, a status interrupt
request (DIRR.STI) is generated and the µC has to set ESP0 to
acknowledge the status phase.
• Data transfer Host => Device:
• Data transfer Device => Host:
If the status phase is successfully completed, bit ESP0 is automatically
reset by the UDC.
Additionally, the ESP0 bit is cleared with every setup frame.
If the CPU detects a corrupted control transfer, bit STALL0 should be set
by software instead of bit ESP0 in order to indicate an error condition
from which the USB device can not recover by itself.
The SOD0 bit is set at the end of a status-in transfer.
Set Direction of USB Memory Buffer to Read
Bit SETRDn is used to predict the direction of the next USB access for
endpoint n as a USB read access. A faulty prediction causes no errors
since the USB module determines the real direction. A change in the data
direction is only executed if both USB memory buffers are empty.
SETRDn can not be set together with CLREPn because a change of bit
DIRn during a transfer is not allowed.
Note: bits SETRDn and SETWRn must not be set at the same time.
Set Direction of USB Memory Buffer to Write
Bit SETWRn is used to predict the direction of the next USB access for
endpoint n as a USB write access. A faulty prediction causes no errors
since the USB module determines the real direction. A change in the data
direction is only executed if both USB memory buffers are empty.
SETWR can not be set together with CLREPn because a change of
EPBSn.DIRn during a transfer is not allowed.
Note: bits SETWRn and SETRDn must not be set at the same time.
After the host has transmitted the last valid data packet, the UDC will
automatically transmit a zero data packet to the host if ESP0is set.
After the UDC has transmitted the last valid data packet and the host
has responded with a zero data packet, the UDC will automatically
transmit an ACK to the host if ESP0 is set.
578
USB Module
PSB 21473
2003-03-31
INCA-D