PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 113

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

After an interrupt service routine has been terminated by executing the RETI instruction,
and if further interrupts are pending, the next interrupt service routine will not be entered
until at least two instruction cycles have been executed of the program that was
interrupted. In most cases two instructions will be executed during this time. Only one
instruction will typically be executed, if the first instruction following the RETI instruction
is a branch instruction (without cache hit), or if it reads an operand from internal code
memory, or if it is executed out of the internal RAM.
Note: A bus access in this context includes all delays which can occur during an external
8.8
The PEC response time defines the time from an interrupt request flag of an enabled
interrupt source being set until the PEC data transfer being started. The basic PEC
response time for the INCA-D is 2 instruction cycles.
•
Figure 8-9
In Figure 8-9 the respective interrupt request flag is set in cycle 1 (fetching of instruction
N). The indicated source wins the prioritization round (during cycle 2). In cycle 3 a PEC
transfer “instruction” is injected into the decode stage of the pipeline, suspending
instruction N+1 and clearing the source's interrupt request flag to '0'. Cycle 4 completes
the injected PEC transfer and resumes the execution of instruction N+1.
All instructions that entered the pipeline after setting of the interrupt request flag (N+1,
N+2) will be executed after the PEC data transfer.
Note: When instruction N reads any of the PEC control registers PECC7...PECC0, while
Data Sheet
Pipeline Stage
FETCH
DECODE
EXECUTE
WRITEBACK
IR-Flag
bus cycle.
a PEC request wins the current round of prioritization, this round is repeated and
the PEC data transfer is started one cycle later.
PEC Response Times
Pipeline Diagram for PEC Response Time
1
0
Cycle 1
N
N - 1
N - 2
N - 3
PEC Response Time
Cycle 2
N + 1
N
N - 1
N - 2
113
Cycle 3
N + 2
PEC
N
N - 1
Cycle 4
N + 2
N + 1
PEC
N
PSB 21473
Interrupts
2003-03-31
INCA-D