PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 211

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

The event causing an increment or decrement of the timer can be a positive, a negative,
or both a positive and a negative transition at either the input line, or at the toggle latch
T6OTL.
Bit field T5P in control register T5CON selects the triggering transition (see table below).
Table 14-9
T5P
X 0 0
0 0 1
0 1 0
0 1 1
1 0 1
1 1 0
1 1 1
Note: Only state transitions of T6OTL which are caused by the overflows/underflows of
The maximum input frequency which is allowed in counter mode is f
To ensure that a transition of the count input signal which is applied to T5IN is correctly
recognized, its level should be held high or low for at least 2 f
before it changes.
14.2.3
Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode
concatenates the core timer T6 with the auxiliary timer. Depending on which transition of
T6OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a 33-
bit timer / counter.
l 32-bit Timer/Counter: If both a positive and a negative transition of T6OTL is used to clock the
l 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL is selected to clock the
The count directions of the two concatenated timers are not required to be the same.
This offers a wide variety of different configurations.
T6 can operate in timer, gated timer or counter mode in this case.
Data Sheet
auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T6. Thus, the
two timers form a 32-bit timer.
auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T6.
This configuration forms a 33-bit timer (16-bit core timer+T6OTL+16-bit auxiliary timer).
T6 will trigger the counter function of T5. Modifications of T6OTL via software will
NOT trigger the counter function of T5.
Timer Concatenation
Auxiliary Timer (Counter Mode) Input Edge Selection
Triggering Edge for Counter Increment / Decrement
None. Counter T5 is disabled
Positive transition (rising edge) on T5IN
Negative transition (falling edge) on T5IN
Any transition (rising or falling edge) on T5IN
Positive transition (rising edge) of output toggle latch T6OTL
Negative transition (falling edge) of output toggle latch T6OTL
Any transition (rising or falling edge) of output toggle latch T6OTL
211
General Purpose Timer Unit
Timer
cycles (FM2 = ’1’)
Timer
/4 (FM2 = ’1’).
PSB 21473
2003-03-31
INCA-D