PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 584

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
Power Reduction Modes
For wake-up an internal logic uses the rising edge of interrupt node 13, which should
represent the Level Detect interrupt of ithe transceiver.
This means for a proper wake-up from the line the interrupt status register IRQ13_STA
carries the LD (Level Detect) interrupt of the line transceiver only, ie. all other interrupts
have to be masked. (see Figure 8-3).
23.2
Idle Mode of the CPU
The power consumption of the INCA-D microcontroller can be decreased by entering
Idle mode. In this mode all peripherals, including the watchdog timer, continue to
operate normally, only the CPU operation is halted.
Idle mode is entered after the IDLE instruction has been executed and the instruction
before the IDLE instruction has been completed. To prevent unintentional entry into Idle
mode, the IDLE instruction has been implemented as a protected 32-bit instruction.
Idle mode is terminated by interrupt requests from any enabled interrupt source whose
individual Interrupt Enable flag was set before the Idle mode was entered, regardless of
bit IEN.
For a request selected for CPU interrupt service the associated interrupt service routine
is entered if the priority level of the requesting source is higher than the current CPU
priority and the interrupt system is globally enabled. After the RETI (Return from
Interrupt) instruction of the interrupt service routine is executed the CPU continues
executing the program with the instruction following the IDLE instruction. Otherwise, if
the interrupt request cannot be serviced because of a too low priority or a globally
disabled interrupt system the CPU immediately resumes normal program execution with
the instruction following the IDLE instruction.
For a request which was programmed for PEC service a PEC data transfer is performed
if the priority level of this request is higher than the current CPU priority and the interrupt
system is globally enabled. After the PEC data transfer has been completed the CPU
remains in Idle mode. Otherwise, if the PEC request cannot be serviced because of a
too low priority or a globally disabled interrupt system the CPU does not remain in Idle
mode but continues program execution with the instruction following the IDLE
instruction.
Data Sheet
584
2003-03-31