PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 103

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

PSW (FF10
Bit
N, C, V,
Z, E,
MULIP
ILVL
IEN
CPU Priority ILVL defines the current level for the operation of the CPU. This bit field
reflects the priority level of the routine that is currently executed. Upon the entry into an
interrupt service routine this bit field is updated with the priority level of the request that
is being serviced. The PSW is saved on the system stack before. The CPU level
determines the minimum interrupt priority level that will be serviced. Any request on the
same or a lower level will not be acknowledged. The current CPU priority level may be
adjusted via software to control which interrupt request sources will be acknowledged.
PEC transfers do not really interrupt the CPU, but rather “steal” a single cycle, so PEC
services do not influence the ILVL field in the PSW.
Hardware traps switch the CPU level to maximum priority (ie. 15) so no interrupt or PEC
requests will be acknowledged while an exception trap service routine is executed.
Note: The TRAP instruction does not change the CPU level, so software invoked trap
Interrupt Enable bit IEN globally enables or disables PEC operation and the
acceptance of interrupts by the CPU. When IEN is cleared, no interrupt requests are
accepted by the CPU. When IEN is set to '1', all interrupt sources, which have been
Data Sheet
service routines may be interrupted by higher requests.
15
7
0
r
Function
CPU status flags (Described in section “The Central Processing Unit”,
page 53).
Define the current status of the CPU (ALU, multiplication unit).
CPU Priority Level
Defines the current priority level for the CPU
F
0
Interrupt Enable Control Bit (globally enables/disables interrupt requests)
‘0’: Interrupt requests are disabled
‘1’: Interrupt requests are enabled
H
H
H
/ 88
: Lowest priority level
: Highest priority level
H
)
14
6
0
r
ILVL
rw
MULIP
13
rw
5
12
rw
E
4
SFR
103
IEN
11
rw
rw
3
Z
10
rw
V
0
2
r
Reset Value: 00
rw
C
9
0
1
r
PSB 21473
Interrupts
2003-03-31
H
INCA-D
rw
N
8
0
0
r