PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 275

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PSB21473FV13XT

Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21473FV13XT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
INCA-D
PSB 21473
IOM-2 Handler, TIC/CI Handler and HDLC Controller
If the SWAP bit = ’0’ (swap is disabled) the time slot and data port for the input and output
of the CDAxy register is defined by its own TSDPxy register.
If the SWAP bit = ’1’ (swap is enabled) the input port and timeslot of the CDAx0 is defined
by the TSDP register of CDAx1 and the input port and timeslot of CDAx1 is defined by
the TSDP register of CDAx0. The input definition for time slot and data port CDAx0 are
thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output timeslots are
not affected by SWAP.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained
17.1.2.1 Looping and Shifting Data
Figure 17-4 gives examples for typical configurations with the above explained control
and configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers
TSDPxy or CDAx_CR:
a) looping IOM-2 time slot data from DU to DD or vice versa (SWAP = 0)
b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP
= 1)
c) switching data from TSa to TSb and looping from DU to DD or switching TSc to TSd
and looping from DD to DU respectively
Data Sheet
275
2003-03-31

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