PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 161

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
The External Bus Interface
must have been latched externally, the address is removed from the bus. The EBC now
activates the respective command signal (RD, WR, WRL, WRH). Data is driven onto the
bus either by the EBC (for write cycles) or by the external memory/peripheral (for read
cycles). After a period of time, which is determined by the access time of the memory/
peripheral, data become valid.
Read cycles: Input data is latched and the command signal is now deactivated. This
causes the accessed device to remove its data from the bus which is then tri-stated
again.
Write cycles: The command signal is now deactivated. The data remain valid on the bus
until the next external bus cycle is started.
Figure 11-2 Multiplexed Bus Cycle
The bus cycle is described in number of TCL’s, where f
= 1/(2 TCL).
CPU
Demultiplexed Bus Modes
In the demultiplexed bus modes the 16-bit intra-segment address is permanently output
on PORT1, while the data uses PORT0 (16-bit data) or P0L (8-bit data).
The upper address lines are permanently output on Port 4 (if selected via SALSEL during
reset). No address latches are required.
The EBC initiates an external access by placing an address on the address bus. After a
programmable period of time the EBC activates the respective command signal (RD,
WR, WRL, WRH). Data is driven onto the data bus either by the EBC (for write cycles)
Data Sheet
161
2003-03-31