PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 246

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
data bits are transmitted synchronous with the shift clock. After the bit time for the 8th
data bit, both TXD and RXD will go high, the transmit interrupt request line TIR is
activated, and serial data transmission stops.
Pin P3.10/TXD must be configured for alternate data output in order to provide the shift
clock. Pin P3.11/RXD must also be configured for output during transmission.
15.1.6.2 Synchronous Reception
Synchronous reception is initiated by setting bit S0CON_REN=’1’. If bit S0CON_R=1,
the data applied at RXD is clocked into the receive shift register synchronous to the clock
which is output at pin TXD. After the 8th bit has been shifted in, the content of the receive
shift register is transferred to the receive data buffer RBUF, the receive interrupt request
line RIR is activated, the receiver enable bit S0CON_REN is reset, and serial data
reception stops.
Pin P3.10/TXD must be configured for alternate data output in order to provide the shift
clock. Pin P3.11/RXD must be configured as alternate data input.
Synchronous reception is stopped by clearing bit S0CON_REN. A currently received
byte is completed including the generation of the receive interrupt request and an error
interrupt request, if appropriate. Writing to the transmit buffer register while a reception
is in progress has no effect on reception and will not start a transmission.
If a previously received byte has not been read out of the receive buffer register at the
time the reception of the next byte is complete, both the error interrupt request line EIR
and the overrun error status flag S0CON_OE will be activated/set, provided the overrun
check has been enabled by bit S0CON_OEN.
15.1.6.3 Synchronous Timing
Figure 15-10 shows timing diagrams of the ASC synchronous mode data reception and
data transmission. In idle state the shift clock is at high level. With the beginning of a
synchronous transmission of a data byte the data is shifted out at RXD with the falling
edge of the shift clock. If a data byte is received through RXD data is latched with the
rising edge of the shift clock.
Between two consecutive receive or transmit data bytes one shift clock cycle (f
is inserted.
The Asynchronous / Synchr. Serial Interface
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PSB 21473
2003-03-31
INCA-D
BR
) delay