PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 160

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
11.1
When the external bus interface is enabled (bit BUSACTx=’1’) and configured (bitfield
BTYP), the INCA-D uses a subset of its port lines together with some control lines to
build the external bus.
The bus configuration (BTYP) for the address windows (BUSCON4...BUSCON1) is
selected via software typically during the initialization of the system.
The bus configuration (BTYP) for the default address range (BUSCON0) is selected via
PORT0 during reset, otherwise BUSCON0 may be programmed via software just like the
other BUSCON registers.
The address space of the INCA-D is divided into segments of 64 KByte each. The 16-bit
intra-segment address is output on PORT0 for multiplexed bus modes or on PORT1 for
demultiplexed bus modes. When segmentation is disabled, only one 64 KByte segment
is available. Because of the occupied 8 KBytes of memory in segment 0, only 56 can be
used and accessed. Otherwise additional address lines may be output on Port 4, and/or
several chip select lines may be used to select different memory banks or peripherals.
These functions are selected during reset via bitfields SALSEL and CSSEL of register
RP0H, respectively.
Note: Bit SGTDIS of register SYSCON defines, if the CSP register is saved during
Multiplexed Bus Modes
In the multiplexed bus modes the 16-bit intra-segment address as well as the data use
PORT0. The address is time-multiplexed with the data and has to be latched externally.
The width of the required latch depends on the selected data bus width, ie. an 8-bit data
bus requires a byte latch (the address bits A15...A8 on P0H do not change, while P0L
multiplexes address and data), a 16-bit data bus requires a word latch (the least
significant address line A0 is not relevant for word accesses). The upper address lines
(A21...A16) are permanently output on Port 4 (if segmentation is enabled) and do not
require latches.
The EBC initiates an external access by generating the Address Latch Enable signal
(ALE) and then placing an address on the bus. The falling edge of ALE triggers an
external latch to capture the address. After a period of time during which the address
BTYP Encoding External Data Bus Width
interrupt entry (segmentation active) or not (segmentation disabled).
0 0
0 1
1 0
1 1
External Bus Modes
8-bit Data
8-bit Data
16-bit Data
16-bit Data
160
External Address Bus Mode
Demultiplexed Addresses
Multiplexed Addresses
Demultiplexed Addresses
Multiplexed Addresses
The External Bus Interface
PSB 21473
2003-03-31
INCA-D