MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 926

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RISC Microcode from RAM
C.2.3 Performance
At 25Mhz, an MGCI serial bit rate of 2 Mbps on one SCC consumes 20 - 25% of the pro-
cessing power of the RISC communications engine. An MGCI SCC operating at a serial bit
rate of 2Mbps carries 32 x 64Kbit channels, Table C-2 shows possible QUICC configuration.
C.3 ATOM1/ATM CONTROLLER
ATOM1 provides physical layer ATM functions by converting one or more of the QUICC’s
Serial Communication Controllers (SCCs) into an ATM cell transmitter and receiver. The
microcode provides the user with basic cell streaming facilities (cell reception and transmis-
sion) and event indications. The primary application of ATOM1 is intended to be plesiochro-
nous digital hierarchy (PDH) and synchronous digital hierarchy (SDH) E1 and DS1 ATM
equipment. Such equipment is used for signalling and low rate data transfer.
Figure C-2 shows an ATM / frame relay interworking system as may be used in remote
bridging applications. Using the Ethernet channel available on the QUICC, remote LAN
bridging equipment can be constructed to link remote Ethernet LANs over E1 telecommuni-
cations links.
C.3.1 Key Features
C-4
• All receive data is timestamped.
• Handles 2, 4, 8, or 16 ISDN lines with full C/I and monitor channel functions.
• Handles up to 32 ISDN lines with only C/I channels.
• Simultaneous detection of multiple C/I code changes and transmission changes.
• Maskable interrupts generated for many events.
• Handles GCI monitor messages from 1 to 64 Kilobytes in length.
• Monitor receiver can be locked into a particular channel.
• Monitor receiver and transmitter include timers to prevent lockup due to inactivity.
• Operates independently of user CPU activity.
• Consumes 1280 bytes of the QUICC’s internal memory.
• Cell transmission and reception for all AAL protocols.
• Transmit and receive data buffers located in main memory.
• Microcode constructs the cell header and appends user defined payload on transmit.
• Microcode verifies cell headers and strips HEC before passing cell to the user on re-
ceive.
MGCI SCCs
1 x 2 Mbit/s
2 x 2 Mbit/s
Freescale Semiconductor, Inc.
Risc Bandwidth
Consumed (est)
Table C-2. MGCI SCC Configuration
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MC68360 USER’S MANUAL
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3 x 2 Mbit HDLC, 2 x 9.6 Kbit SMC UART
2 x 2 Mbit HDLC, 2 x 9.6 Kbit SMC UART
Possible Configuration of Other Channels