MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 57

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

2.1.7.7 OUTPUT ENABLE/ADDRESS MULTIPLEX (OE/AMUX). This pin can be pro-
grammed as the output enable (OE) output or as the address multiplex output.
OE—During a read cycle, this output signal is driven by the bus master to indicate that an
external device should place valid data on the data bus. OE may used to save an external
inversion of the R/W signal.
AMUX—This output signal is driven by the DRAM controller to the external address multi-
plexer. AMUX need not be used if the DRAM addresses are multiplexed internally by the
QUICC.
2.1.7.8 BYTE WRITE ENABLE (WE3–WE0) . See 2.1.1.2 Address Bus (A31–A28) for the
description.
2.1.8 Bus Arbitration Signals
The following signals are the four bus arbitration control signals used to determine the bus
master. Refer to Section 4 Bus Operation for more information concerning these signals.
2.1.8.1 BUS REQUEST (BR). This active-low input signal indicates that an external device
needs to become the bus master. This input is typically wire-ORed.
2.1.8.2 BUS GRANT (BG). Assertion of this active-low output signal indicates that the bus
master has relinquished the bus.
2.1.8.3 BUS GRANT ACKNOWLEDGE (BGACK). Assertion of this active-low input indi-
cates that an external device has become the bus master.
2.1.8.4 READ-MODIFY-WRITE CYCLE/INITIAL CONFIGURATION (RMC/CONFIG0).
This pin can be programmed as the read-modify-write cycle output or as the initial configu-
ration pin 0 input signal during system reset.
RMC—This output signal identifies the bus cycle as part of an indivisible read-modify-write
operation; it remains asserted during all bus cycles of the read-modify-write operation to
indicate that bus ownership cannot be transferred.
CONFIG0—See 2.1.13 Initial Configuration Pins (CONFIG) for the description.
2.1.8.5 BUS CLEAR OUT/INITIAL CONFIGURATION/ROW ADDRESS SELECT
DOUBLE-DRIVE (BCLRO/CONFIG1/RAS2DD). This pin can be programmed as the bus
clear out output or as the initial configuration pin 1 input signal during system reset or as the
RAS2DD output double-drive signal.
RMC is muxed with a CONFIG0 pin. RMC only functions when
the CPU32+ is enabled, and is an output unless an external
master ownes the bus, in which case it is an input.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Signal Descriptions