MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 547

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.10.21.4 ACHIEVING SYNCHRONIZATION IN TRANSPARENT MODE. Once the SCC
transmitter is enabled for transparent operation in the GSMR, the Tx BD is prepared for the
SCC, and the transmit FIFO has been preloaded by the SDMA channel, one additional pro-
cess must occur before data can be transmitted—i.e., transmit synchronization.
Similarly, once the SCC receiver is enabled for transparent operation in the GSMR and the
Rx BD is made empty for the SCC, one additional process must occur before data can be
received—receive synchronization.
The synchronization process gives the user bit-level control over when the transmission and
reception can begin. There are two basic methods: an in-line synchronization pattern and
external synchronization signals.
7.10.21.4.1 In-Line Synchronization Pattern. The transparent channel can be pro-
grammed to transmit and receive a synchronization pattern if the SYNL bits in the GSMR
are non-zero. The pattern is defined in the DSR. The length of the SYNC pattern is defined
in the SYNL bits in the GSMR.
The receiver synchronizes on the synchronization pattern that is located in the DSR. For
instance, if a 4-bit SYNC is selected, then reception begins as soon as these four bits are
received, beginning with the first bit following the 4-bit SYNC.
The transmitter can synchronize on the receiver pattern if the RSYN bit in the GSMR is set.
This effectively links the transmitter synchronization to the receiver synchronization.
External Synchronization Signals
If the SYNL bits in the GSMR are programmed to 00, an external signal is used to begin the
sequence. The CTS pin is used for the transmitter, and the CD pin is used for the receiver.
The CD and CTS pins share two options: the pulse option and the sampling option.
The pulse option determines whether the CD pin or CTS pins need only be asserted once
to begin reception/transmission or whether the CD pin or CTS pins must be asserted and
stay asserted for the duration of the transparent frame. This is controlled by the CDP and
CTSP bits in the GSMR. If the user expects a continuous stream of data without interruption,
then the pulse operation should be used. However, if the user is trying to identify frames of
transparent data, then the envelope mode of the CD and CTS pins should be used.
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4-BIT SYNC
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The MC68302 transparent mode offered the EXSYN bit, which,
when set, gave the pulse behavior.
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8-BIT SYNC
Freescale Semiconductor, Inc.
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For More Information On This Product,
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MC68360 USER’S MANUAL
Go to: www.freescale.com
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16-BIT SYNC
NOTE
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Serial Communication Controllers (SCCs)
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