MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 541

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

TXE—Tx Error
RCH—Receive Character
BSY—Busy Condition
TX—Tx Buffer
RX—Rx Buffer
7.10.20.15 BISYNC MASK REGISTER (SCCM). The SCCM is referred to as the BISYNC
mask register when the SCC is operating as a BISYNC controller. It is a 16-bit read-write
register that has the same bit format as the BISYNC event register. If a bit in the BISYNC
mask register is a one, the corresponding interrupt in the event register will be enabled. If
the bit is zero, the corresponding interrupt in the event register will be masked. This register
is cleared upon reset.
7.10.20.16 SCC STATUS REGISTER (SCCS). The SCCS is an 8-bit read-only register that
allows the user to monitor real-time status conditions on the RXD line. The real-time status
of the CTS and CD pins are part of the port C parallel I/O.
CS—Carrier Sense (DPLL)
7.10.20.17 PROGRAMMING THE BISYNC CONTROLLER. There are two general tech-
niques that the software may employ to handle data received by the BISYNC controllers.
The simplest way is to allocate single-byte receive buffers, request (in the status word in
each BD) an interrupt on reception of each buffer (i.e., byte), and implement the BISYNC
protocol entirely in software on a byte-by-byte basis. This simple approach is flexible and
may be adapted to any BISYNC implementation. The obvious penalty is the overhead
caused by interrupts on each received character.
sage that was in progress when the command was issued. It will be set immediately if no
message was in progress when the command was issued.
An error (CTS lost or underrun) occurred on the transmitter channel.
A character has been received and written to the buffer.
A character was received and discarded due to lack of buffers. The receiver will resume
reception after an ENTER HUNT MODE command.
A buffer has been transmitted. This bit is set as the last bit of data or the BCS (if sent)
begins transmission.
A receive buffer has been closed by the CP on the BISYNC channel.
This bit shows the real-time carrier sense of the line as determined by the DPLL if it is
used.
0 = The DPLL does not sense a carrier.
1 = The DPLL does sense a carrier.
Freescale Semiconductor, Inc.
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For More Information On This Product,
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MC68360 USER’S MANUAL
Go to: www.freescale.com
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Serial Communication Controllers (SCCs)
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CS
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