MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 277

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

BCLRISM2–BCLRISM0—Bus Clear Interrupt Service Mask (Normal Mode Only)
BCLRIID2–BCLRIID0—Bus Clear In Arbitration ID (Slave Mode Only)
IARB3–IARB0—Interrupt Arbitration
These bits contain the interrupt service mask. When the interrupt service level on the IMB
is greater than the interrupt service mask, the BCLRO signal will be asserted until the in-
terrupt level is less than or equal to the interrupt service mask. This feature can be used
to clear an external master from the external bus to reduce the interrupt latency for a cer-
tain interrupt level and above.
These bits contain the arbitration priority level for the BCLRI signal. If BCLRI is asserted
when the internal master (IDMA, SDMA, or DRAM refresh cycle) is requesting or using
the bus, and if the arbitration level on the IMB is lower than the bus clear in arbitration ID
bits, the internal master will release the bus until the BCLRI signal is negated. Thus, BCL-
RI can be used to clear an internal master from the external bus when the bus is needed
for a higher priority task.
The reset value of IARB is $F, allowing the SIM60 to win interrupt arbitrations during an
interrupt acknowledge cycle immediately after reset. The system software should initialize
the IARB field to a value from $F (highest priority) to $1 (lowest priority).
This bit is “don’t care” in the SIM60 since no user space registers
exist. It is reserved for future expansions.
This value should be programmed to 7 in a typical system unless
the user needs to give certain interrupt routines priority over ex-
ternal bus masters.
In slave mode (disable CPU32+), these bits are not used and
have a different definition.
Program the arbitration IDs of the QUICC as follows: SDMA = 4,
IDMAx = 2, IDMAy = 0. The DRAM refresh controller is always
6. Thus, the user may choose 3 for this value to give the external
master priority over the IDMA channels only.
In the case of the MC68040 companion mode, the BG pin is also
negated by the QUICC when an internal master has released
the bus.
In normal operation (CPU32+ enabled), these bits are not used
and have a different definition.
This field should never be programmed to be 7.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
NOTES
NOTE
System Integration Module (SIM60)