MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 618

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Management Controllers (SMCs)
Once the REN bit is set in SMCMR, the first rising edge of SMCLK that detects the SMSYNx
pin as low causes the SMC receiver to achieve synchronization. Data will begin to be
received (latched) on the same rising edge of SMCLK that latched SMSYNx. This will be the
first bit of data received. The receiver will never lose synchronization again, regardless of
the state of SMSYNx, until the REN bit is cleared by the user.
Once the TEN bit is set in SMCMR, the first rising edge of SMCLK that detects the SMSYNx
pin as low causes the SMC transmitter to achieve synchronization. The SMC transmitter will
begin transmitting ones asynchronously from the falling edge of SMSYNx. After one char-
acter of ones is transmitted, if the transmit FIFO is loaded (i.e., the Tx BD was ready with
7-294
SMSYN
Regardless of whether the transmitter or receiver uses the SM-
SYNx signal, the SMSYNx signal must make glitch-free transi-
tions from high to low or low to high. Glitches on SMSYNx may
cause errant behavior of the SMC.
SMCLK
SMRXD
SMSYN
SMTXD
SMCLK
NOTES:
1. SMCLK is an internal clock derived from an external CLKPIN or a baud rate generator.
2. This example shows the SMC receiver and transmitter enabled separately. If the REN
HUNT MODE
COMMAND
HERE OR
REN SET
and TEN bits were set at the same time, a single falling edge of SMSYN would
synchronize both.
ENTER
ISSUED
Figure 7-78. Synchronization with the SMSYNx Pin
HERE
TEN
SET
1's ARE SENT
Freescale Semiconductor, Inc.
DETECTED
LOW HERE
SMSYN
For More Information On This Product,
DETECTED
LOW HERE
SMSYN
MC68360 USER’S MANUAL
Go to: www.freescale.com
LOADED
TX FIFO
APPX.
HERE
FIVE 1's ARE SENT
FIRST BIT OF
DATA (LSB)
RECEIVE
NOTE
CHARACTER
EQUALS 5
ASSUME
LENGTH
FIVE 1's
SMC1 RECEIVE DATA
FIRST BIT OF
CHARACTER
SMC1 TRANSMIT DATA
FIRST 5-BIT
TRANSMIT
(LSB)
HERE IF TX FIFO
NOT LOADED IN
TRANSMISSION
COULD BEGIN
TIME