MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 357

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.6.2.8 CHANNEL MASK REGISTER (CMAR). The CMAR is an 8-bit, memory-mapped,
read-write register that has the same bit format as the CSR. If a bit in the CMAR is a one,
the corresponding interrupt in the CSR will be enabled. If the bit is a zero, the corresponding
interrupt in the CSR will be masked. CMAR is cleared at reset.
7.6.2.9 DATA HOLDING REGISTER (DHR). This 7-byte register serves as a buffer register
for the data being transferred during dual address IDMA cycles. No address for DHR is given
since this register cannot be addressed by the programmer. The DHR allows the data to be
packed and unpacked by the IDMA during the transfer. For example, if the source operand
size is byte and the destination operand size is word, then two-byte read cycles occur, fol-
lowed by a one-word write cycle. The two bytes of data are buffered in the DHR until the
word write cycle occurs. The DHR allows for packing and unpacking of operands for all pos-
sible combinations: bytes to words, bytes to long words, words to long words, words to
bytes, long words to bytes, and long words to words.
7.6.3 Interface Signals
The IDMA has three dedicated control signals per channel: DMA request (DREQx), DMA
acknowledge (DACKx), and end of IDMA transfer (DONEx). The peripheral used with these
signals may be either a source or a destination of the IDMA transfers.
7.6.3.1 DREQ AND DACK. These are the handshake signals between the peripheral
requiring service and the QUICC. When the peripheral requires IDMA service, it asserts
DREQx, and the QUICC begins the IDMA process. When the IDMA service is in progress,
DACKx is asserted during accesses to the device. DREQx is ignored when the IDMA is pro-
grammed to one of the internal request modes.
7.6.3.2 DONEX. This bidirectional open-drain signal is used to indicate the last IDMA trans-
fer. DONEx is always an output of the IDMA if the transfer count is exhausted.
DONEx may also operate as an input. If DONEx is externally asserted during internal
request modes, the IDMA transfer is terminated. With external request modes, DONEx may
be used as an input to the IDMA controller to indicate that the device being serviced requires
no more transfers and the transmission is to be terminated.
2. In buffer chaining or auto buffer modes, the BCR has decremented to zero, the L-bit
3. An external peripheral has asserted DONEx during an access by the IDMA to that
DONE will not be set if the channel terminates due to an error. DONE is cleared by writing
a one or by setting RST in the CMR. Writing a zero has no effect on DONE.
in the BD has been set, and no errors have occurred during any IDMA transfer bus
cycle.
peripheral and no errors have occurred during any IDMA transfer bus cycle.
DREQ must be level sensitive if IDMA uses buffer chaining
mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
IDMA Channels