MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 881

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10.23 SI ELECTRICAL SPECIFICATIONS
(The electrical specifications in this document are preliminary. See Figure 10-60–Figure 10-64.)
NOTES:
1. The ratio SyncCLK/L1RCLK must be greater than 2.5/1
2. Where P=1/CLKO1. Thus for a 25 MHz CLKO1 rate, P=40ns.
3. These specs are valid for IDL mode only
4. The strobes and Txd on the first bit of the frame become valid after L1CLK edge or L1SYNC,
Num.
70
71A
78A
80A
83A
71
85
86
87
72
73
74
75
76
77
78
79
80
81
82
83
84
88
whichever is later.
1,3
3
3
3
3
2
4
4
2
L1CLK edge to L1ST(1–4) Valid
L1SYNC Valid to L1ST(1–4) Valid
L1CLK Edge to L1ST(1–4) Invalid
L1CLK edge to L1SYNC Valid
(FSD = 00, CNT = 0000, BYT = 0, DSC=0)
L1RCLK, L1TCLK Fequency (DSC=0)
L1RCLK, L1TCLK Width Low(DSC=0)
L1RCLK, L1TCLK Width High (DSC=0)
L1TXD, L1ST(1–4), L1RQ, L1CLKO Rise/Fall
Time
L1RSYNC, L1TSYNC Valid to L1CLK edge
(SYNC Setup Time)
L1CLK edge to L1RSYNC, L1TSYNC Invalid
(SYNC Hold Time)
L1RSYNC, L1TSYNC Rise/Fall Time
L1RXD Valid to L1CLK edge (L1RXD Setup
Time)
L1CLK edge to L1RXD Invalid (L1RXD Hold
Time)
L1CLK Edge to L1TXD Valid
L1TSYNC Valid to L1TXD Valid
L1CLK Edge to L1TXD High Impedance
L1RCLK, L1TCLK Fequency (DSC=1)
L1RCLK, L1TCLK Width Low(DSC=1)
L1RCLK, L1TCLK Width High (DSC=1)
L1CLK Edge to L1CLKO Valid (DSC=1)
L1RQ Valid Before Falling Edge of L1TSYNC
L1GR Setup Time
L1GR Hold Time
Freescale Semiconductor, Inc.
For More Information On This Product,
Characteristic
MC68360 USER’S MANUAL
Go to: www.freescale.com
3.3 V or 5.0 V
P+10
P+10
P+10
P+10
Min
20
35
42
35
42
42
—
—
—
10
10
10
10
10
—
—
—
25.0 MHz
0
1
Max
12.5
10
15
15
45
45
45
65
65
42
30
—
—
—
—
—
—
—
—
—
—
—
0
P+10
P+10
P+10
P+10
Min
33.34 MHz
—
—
20
35
—
42
35
10
10
10
10
10
—
—
42
42
—
0
1
5.0 V
Electrical Characteristics
Max
10
15
15
45
45
45
65
65
42
16
30
—
—
—
—
—
—
—
—
—
—
—
0
L1TCLK
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns