MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 502

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
CRC Error . When this error occurs, the channel writes the received CRC to the data buffer,
closes the buffer, sets the CR bit in the Rx BD, and generates the RXF interrupt (if enabled).
The channel also increments the CRC error counter. After receiving a frame with a CRC
error, the receiver enters hunt mode. (An immediately following back-to-back frame will still
be received.) CRC checking cannot be disabled, but the CRC error may be ignored if check-
ing is not required.
7.10.17.8 HDLC MODE REGISTER (PSMR). Each HDLC mode register is a 16-bit, mem-
ory-mapped, read-write register that controls SCC operation. The term HDLC mode register
refers to the PSMR of the SCC when that SCC is configured for HDLC. The HDLC mode
register is cleared at reset.
NOF—Number of Flags
CRC—CRC Selection
RTE—Retransmit Enable
Bits 8, 2–0—Reserved
FSE—Flag Sharing Enable
7-178
15
Minimum number of flags between frames or before frames (0 to 15 flags). If NOF = 0000,
then no flags will be inserted between frames. Thus, the closing flag of one frame will be
immediately followed by the opening flag of the next frame in the case of back-to-back
frames. These bits may be modified on the fly.
This bit is only valid if the RTSM bit is set in GSMR This bit may be modified on the fly.
00 = 16-Bit CCITT-CRC (HDLC). (X16 + X12 + X5 + 1)
01 = Reserved.
10 = 32-Bit CCITT-CRC (Ethernet and HDLC). (X32 + X26 + X23 + X22 + X16 + X12
11 = Reserved.
0 = No retransmission
1 = Automatic frame retransmission is enabled. This is particularly useful in the HDLC
0 = Normal operation
1 = If NOF3–NOF0 = 0000, then a single shared flag is transmitted between back-to-
14
Bus protocol and ISDN applications where multiple HDLC controllers may be col-
liding on a single channel. Note that retransmission only occurs if the CTS lost hap-
pens on the first or second buffer of the frame.
back frames. Other values of NOF3–NOF0 are decremented by one when FSE is
set. This is useful in Signaling System #7 applications.
NOF
+ X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1)
13
12
11
Freescale Semiconductor, Inc.
CRC
For More Information On This Product,
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
RTE
9
—
8
FSE
7
DRT
6
BUS
5
BRM
4
MFF
3
2
—
1
0