MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 198

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
exception frame on top of the stack, and resume execution at the exception handler
address.
5.5.4 CPU32+ Stack Frames
The CPU32+ generates three different stack frames: four-word frames, six-word frames,
and twelve-word bus error frames.
5.5.4.1 FOUR-WORD STACK FRAME. This stack frame is created by interrupt, format
error, TRAP #n, illegal instruction, A-line and F-line emulator trap, and privilege violation
exceptions. Depending on the exception type, the PC value is either the address of the next
instruction to be executed or the address of the instruction that caused the exception (see
Figure 5-12).
5.5.4.2 SIX-WORD STACK FRAME. This stack frame (see Figure 5-13) is created by
instruction-related traps, which include CHK, CHK2, TRAPcc, TRAPV, and divide-by-zero,
and by trace exceptions. The faulted instruction PC value is the address of the instruction
that caused the exception. The next PC value (the address to which RTE returns) is the
address of the next instruction to be executed.
Hardware breakpoints also utilize this format. The faulted instruction PC value is the address
of the instruction executing when the breakpoint was sensed. Usually this is the address of
the instruction that caused the breakpoint, but, because released writes can overlap follow-
ing instructions, the faulted instruction PC may point to an instruction following the instruc-
tion that caused the breakpoint. The address to which RTE returns is the address of the next
instruction to be executed.
5.5.4.3 BUS ERROR STACK FRAME. This stack frame is created when a bus cycle fault
is detected. The CPU32+ bus error stack frame differs significantly from the equivalent stack
5-56
+$06
+$06
+$08
SP
+$02
+$02
SP
15
15
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0
Figure 5-12. Format $0—Four-Word Stack Frame
Figure 5-13. Format $2—Six-Word Stack Frame
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Freescale Semiconductor, Inc.
For More Information On This Product,
1
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MC68360 USER’S MANUAL
Go to: www.freescale.com
FAULTED INSTRUCTION PROGRAM COUNTER HIGH
FAULTED INSTRUCTION PROGRAM COUNTER LOW
NEXT INSTRUCTION PROGRAM COUNTER HIGH
NEXT INSTRUCTION PROGRAM COUNTER LOW
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
STATUS REGISTER
STATUS REGISTER
VECTOR OFFSET
VECTOR OFFSET
0
0