MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 166

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
5.3.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five
operations on BCD numbers. The arithmetic operations on packed BCD numbers are add
decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with
extend (NBCD). Table 5-9 is a summary of the BCD operations.
5.3.3.8 PROGRAM CONTROL INSTRUCTIONS. A set of subroutine call and return
instructions and conditional and unconditional branch instructions perform program control
operations. Table 5-10 summarizes these instructions.
5-24
Instruction
Instruction
BCHG
ABCD
NBCD
SBCD
BCLR
BSET
BTST
– (An), – (An)
– (An), – (An)
# data
# data
# data
# data
Table 5-9. Binary-Coded Decimal Operations
Operand
Operand
Dn, ea
Dn, ea
Dn, ea
Dn, ea
Syntax
Syntax
Dn, Dn
Dn, Dn
ea
Table 5-8. Bit Manipulation Operations
Freescale Semiconductor, Inc.
For More Information On This Product,
ea
ea
ea
ea
MC68360 USER’S MANUAL
Go to: www.freescale.com
Operand
Operand
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
Size
Size
8
8
8
8
8
8
~( bit number of destination)
~( bit number of destination)
~( bit number of destination)
~ bit number of destination)
Source 10 + Destination 10 + X
0 – Destination 10 – X
Destination 10 – Source 10 – X
destination
destination
destination
Operation
Operation
Destination
instructions
Z
Z; 0
Z; 1
Z
Destination
Destination
bit of
bit of
bit of
support