MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 353

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RCI — RISC Controls IDMA
REQG — Request Generation
SAPI — SAPR Increment
DAPI — DAPR Increment
SSIZE — Source Size
DSIZE — Destination Size
The REQG bits define what generates the requests for IDMA activity over the bus.
The following decoding shows the definitions for the SSIZE bits. The user should set these
bits to the port size of the source (e.g., choose byte for an 8-bit peripheral).
The following decoding shows the definitions for the DSIZE bits. The user should set
these bits to the port size of the destination (e.g., choose byte for an 8-bit peripheral).
0 = Single Buffer Mode. The user programs all IDMA registers for each buffer transfer.
1 = Auto buffer or buffer chaining mode. The RISC reconfigures the IDMA channel at
00 = Internal request at limited rate (limited burst bandwidth) set by BT bits
01 = Internal request at maximum rate (one burst)
10 = External request burst transfer mode (DREQx is level sensitive)
11 = External request cycle steal (DREQx is edge sensitive)
0 = SAPR is not incremented after each transfer.
1 = SAPR is incremented by one, two, or four after each transfer, according to the
0 = DAPR is not incremented after each transfer.
1 = DAPR is incremented by one, two, or four after each transfer, according to the
00 = Long word
01 = Byte
10 = Word
11 = Reserved
00 = Long word
01 = Byte
10 = Word
11 = Reserved
the end of each buffer transfer according to the buffer descriptor ring. The choice
between auto buffer and buffer chaining is made in the buffer descriptor itself.
SSIZE bits. (SAPR may be incremented by an amount less than the SSIZE value
at the beginning or end of a block transfer, depending on the source starting ad-
dress or byte count.)
DSIZE bits. (DAPR may be incremented by an amount less than the DSIZE value
at the beginning or end of a block transfer, depending on the destination starting
address or byte count.)
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
IDMA Channels