MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 924

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RISC Microcode from RAM
This controller only performs the lowest layers of the SS7 protocol stack. The upper layers
must be performed in software by the CPU in the system. The software to perform the upper
layer protocol is available from third party providers.
The SS7 controller contains the following key features:
C.1.1 Performance
At 25Mhz, an aggregate SS7 bandwidth of 6 Mbps divided among the 4 SCCs consumes
100% of the processing power of the RISC communications engine. If only a percentage of
the total available SS7.
bandwidth is used, the remaining RISC processing power can be used to run other protocols
on other channels. Table C-1 shows possible QUICC configurations.
C-2
• Uses either NMSI or TDM interface and a variety of data encoding schemes.
• Flexible data buffers with multiple buffers per signal unit allowed.
• Separate interrupts for received signal units and transmitted buffers.
• Maintenance of good frame counter, bad frame counter, and SU Error Monitor.
• Standard HDLC features:
—Flag/Abort/Idle generation/detection
—Zero insertion/deletion
—16-bit CRC-CCITT generation/checking
—Detection of non-octet aligned signal units
—Programmable number of flags between signal units
—Detection of long SUs.
—Discard short (less than 5 octets) signal units.
—Automatic Fill-In Signal Unit transmission.
—Automatic Link Status Signal Unit retransmission.
—Automatic discard of identical FISUs and LSSUs.
—Octet Counting Mode support.
—Command to force a reset of filtering state.
—Command to force entry into octet counting mode.
—Ability to permanently disable octet counting mode.
—Ability to disable FISU and LSSU filtering.
—Ability to force entry into octet counting mode if a receiver overrun occurs.
—Consumes 1280 bytes of the QUICC’s internal memory.
SS7 Channels
1 x 64 Kbit/s
2 x 64 Kbit/s
3 x 64 Kbit/s
Freescale Semiconductor, Inc.
Risc Bandwidth
Consumed (est)
For More Information On This Product,
Table C-1. SS7 Configuration
1%
2%
3%
MC68360 USER’S MANUAL
Go to: www.freescale.com
1 x 10 Mbit Ethernet, 2 x 2.048 Mbit HDLC
2 x 4 Mbit HDLC, 2 x 19.2 Kbit SMC UART
1 x 6 Mbit HDLC, 2 x 19.2 Kbit SMC UART
Possible Configuration of Other Channels