MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 546

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
When the end of the current BD has been reached and the L-bit is cleared (working in mul-
tibuffer mode), only the R-bit is cleared, and the transmitter moves immediately to the next
buffer to begin it transmission, with no gap on the serial line between buffers. Failure to pro-
vide the next buffer in time results in a transmit underrun, causing the TXE bit in the trans-
parent event register to be set.
In both cases, an interrupt is issued according to the interrupt (I) bit in the BD. By appropri-
ately setting the I-bit in each BD, interrupts can be generated after the transmission of each
buffer or a after a group of buffers have been transmitted. The SCC will then proceed to the
next BD in the table.
Any whole number of bytes may be transmitted. If the REVD bit in the GSMR is set, each
data byte will be reversed in its bit order before transmission, transmitting the MSB of each
octet first.
An option is available to decrease the latency of the transmitter by decreasing the transmit
FIFO size. This option is enabled by the TFL bit in the GSMR. The user, however, should
note that this option can cause transmitter underruns at higher transmission speeds.
An optional CRC may be appended to each transparent frame if enabled in the Tx BD. The
CRC pattern is chosen in the TCRC bits in the GSMR.
7.10.21.3 TRANSPARENT CHANNEL FRAME RECEPTION PROCESSING. When
the
CPU32+ core enables the SCC receiver in transparent mode, it will wait to achieve synchro-
nization before beginning to receive data. The receiver can be synchronized to the data by
a synchronization pulse or by a SYNC pattern. See 7.10.21.4 Achieving Synchronization in
Transparent Mode for more details.
After a buffer is filled, the SCC clears the empty (E) bit in the BD and generates an interrupt
if the interrupt (I) bit in the BD is set. It then moves to the next Rx BD in the table and begins
moving data to its associated buffer. If the next buffer is not available when needed, a busy
condition is signified by the setting of the BSY bit in the transparent event register, which
can generate a maskable interrupt.
The receiver will revert to the hunt mode upon receiving the ENTER HUNT MODE command
or recognizing an error condition such as a lack of receive buffers, detection of CD lost, or
a receiver overrun.
If the REVD bit in the GSMR is set, each data byte will be reversed in its bit order before it
is written to memory.
An option is available to decrease the latency of the receiver by decreasing the receive FIFO
width. This option is enabled by the RFW bit in the GSMR. The user, however, should note
that this option can cause receiver overruns at higher transmission speeds.
The receiver always checks the CRC of the frame that is received, according to the TCRC
bits in the GSMR. If a CRC is not required, the resulting errors may be ignored.
7-222
MC68360 USER’S MANUAL
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