MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 553

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bits 14, 10, 8, 6, 5, 3—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
L—Last in Frame
F—First in Frame
CM—Continuous Mode
DE—DPLL Error
NO—Rx Nonoctet Aligned Frame
This bit is set by the transparent controller when this buffer is the last in a frame. This im-
plies the negation of CD in envelope mode or the reception of an error, in which case one
or more of the OV, CD, and DE bits are set. The transparent controller will write the num-
ber of frame octets to the data length field.
This bit is set by the transparent controller when this buffer is the first in a frame.
This bit is set by the transparent controller when a DPLL error has occurred during the
reception of this buffer. In Decoding modes where a transition is promised every bit, the
DPLL error will be set when a missing transition occurs.
A frame that contained a number of bits not exactly divisible by eight was received.
1 = The data buffer associated with this BD is empty, or reception is currently in
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been used.
1 = When this buffer has been closed by the transparent controller, the RX bit in the
0 = This buffer is not the last in a frame.
1 = This buffer is the last in a frame.
0 = The buffer is not the first in a frame.
1 = The buffer is the first in a frame.
0 = Normal operation.
1 = The E-bit is not cleared by the CP after this BD is closed, allowing the associated
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E-bit is set, the CPU32+ core should not write any fields of this Rx BD.
receive incoming data into the first BD in the table (the BD pointed to by RBASE).
The number of Rx BD s in this table is programmable and is determined only by
the W-bit and the overall space constraints of the dual-port RAM.
transparent event register will be set. The RX bit can cause an interrupt if it is en-
abled.
data buffer to be overwritten automatically when the CP next accesses this BD.
However, the E-bit will be cleared if an error occurs during reception, regardless of
the CM bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)