MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 581

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

HBC—Heartbeat Checking
FC—Force Collision
RSH—Receive Short Frames
IAM—Individual Address Mode
CRC—CRC Selection
PRO—Promiscuous
BRO—Broadcast Address
SBT—Stop Backoff Timer
0 = No heartbeat checking is performed. Do not wait for a collision after transmission.
1 = Wait 20 transmit clocks (2 s) for a collision asserted by the transceiver after trans-
0 = Normal operation.
1 = Force collision. The channel forces a collision on transmission of every transmit
0 = Discard short frames (less than MINFLR in length)
1 = Receive short frames
0 = Normal operation. A single 48-bit physical address stored in PADDR1 is checked
1 = The individual hash table is used to check all individual addresses that are re-
00 = Reserved.
01 = Reserved.
10 = 32-Bit CCITT-CRC (Ethernet). (X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10
11 = Reserved.
0 = Check the destination address of the incoming frames.
1 = Receive the frame regardless of its address, unless the RRJCT pin is asserted dur-
0 = Receive all frames containing the broadcast address.
1 = Reject all frames containing the broadcast address unless PRO = 1.
0 = The backoff timer functions normally.
1 = The backoff timer (for the random wait after a collision) is stopped whenever carrier
mission. The HB bit in the Tx BD is set if the heartbeat is not heard within 20 trans-
mit clocks.
frame. The QUICC should be configured in loopback operation when using this
feature, which allows the QUICC collision logic to be tested by the user. It will result
in the retry limit being exceeded for each transmit frame.
on receive.
ceived.
ing the frame reception.
sense is active. In this method, the retransmission is less aggressive than the max-
imum allowed in the IEEE 802.3 standard. The persistence (P_Per) feature in the
parameter RAM may be used in combination with the SBT bit (or in place of the
SBT bit), if desired.
+ X8 + X7 + X5 + X4 + X2 + X1 +1). Select this to comply with Ethernet specifica-
tions.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)