MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 192

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
RR—Rerun Write Cycle after RTE
RM—Faulted Cycle Was Read-Modify-Write
IN—Instruction/Other
RW—Read/Write of Faulted Bus Cycle
SIZ—Remaining Size of Faulted Bus Cycle
FUNC—Function Code of Faulted Bus Cycle
5-50
RR will be set if the faulted bus cycle was a released write. A released write is one that is
overlapped. If the write is completed (rerun) in the exception handler, the RR bit should
be cleared before executing RTE. The bus cycle will be rerun if the RR bit is set upon re-
turn from the exception handler.
Faulted RMW bus cycles set the RM bit. RM is ignored during unstacking.
Instruction prefetch faults are distinguished from operand (both read and write) faults by
the IN bit. If IN is cleared, the error was on an operand cycle; if IN is set, the error was on
an instruction prefetch. IN is ignored during unstacking.
Read and write bus cycles are distinguished by the RW bit. Read bus cycles will set this
bit, and write bus cycles will clear it. RW is reloaded into the bus controller if the RR bit is
set during unstacking.
The SIZ field shows operand size remaining when a fault was detected. This field does
not indicate the initial size of the operand, nor does it necessarily indicate the proper sta-
tus of a dynamically sized bus cycle. Dynamic sizing occurs on the external bus and is
transparent to the CPU. Byte size is shown only when the original operand was a byte.
The field is reloaded into the bus controller if the RR bit is set during unstacking. The SIZ
field is encoded as follows:
The function code for the faulted cycle is stacked in the FUNC field of the SSW, which is
a copy of FC2–FC0 for the faulted bus cycle. This field is reloaded into the bus controller
if the RR bit is set during unstacking. All unused bits are stacked as zeros and are ignored
during unstacking. Further discussion of the SSW is included in 5.5.3.1 Types of Faults.
0 = Faulted cycle was read, RMW, or unreleased write
1 = Faulted cycle was a released write
0 = Faulted cycle was non-RMW cycle
1 = Faulted cycle was either the read or write of an RMW cycle
0 = Operand
1 = Prefetch
0 = Faulted cycle was an operand write
1 = Faulted cycle was a prefetch or operand read
00 = Long word
01 = Byte
10 = Word
11 = Unused, reserved
Freescale Semiconductor, Inc.
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