MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 514

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
HDLC bus is based on the techniques used in the CCITT ISDN I.430, and ANSI T1.605 stan-
dards for D-channel point-to-multipoint operation over the S/T interface. However, HDLC
bus is not fully compliant with I.430 or T1.605, and cannot be used to directly
replace devices that implement these protocols. Instead, HDLC bus is more suited to the
needs of non-ISDN LAN and point-to-multipoint configurations.
It may be helpful for the reader to review the basic features of I.430 and T1.605 before learn-
ing HDLC bus.
I.430/T1.605 define a method whereby 8 terminals may be connected over the D-channel
of the S/T bus of ISDN. The protocol used at layer 2 is a variant of HDLC, called LAPD. How-
ever, at layer 1, a method is provided to allow any of the 8 terminals to acquire access to the
physical S/T bus to send frames to the switch.
The S/T interface device detects whether the channel is clear by looking at an "echo" bit on
the line. The echo bit is designed to echo whatever bit was most recently transmitted on the
D channel. Depending on the "class" of the terminal, and the particular situation, the S/T
interface device may wait for 7, 8, 9, or 10 ones on the echo bit before allowing the LAPD
frame to begin transmission. Once transmission begins, the S/T chip monitors the data that
was sent. As long as the echo bit matches the transmit data, the transmission continues. If
the echo bit is ever a zero when the transmit bit is a one, then a collision has occurred
between terminals, and the station(s) that transmitted a zero immediately stops further
transmission. The station that transmitted a one continues normally.
In summary, I.430/T1.605 provides a physical layer protocol that allows multiple terminals
to share the same physical connection. These protocols make very efficient use of the bus
by dealing with collisions in such a way that one station is always able to complete its trans-
mission. Once a station completes a transmission, it lowers its own priority to give other
devices fair access to the physical connection.
HDLC bus works much the same way; however, a few differences exist. First, HDLC bus
does not use the echo bit, but rather a separate pin (CTS) to monitor the data that was trans-
mitted. The transmit data is simply connected to the CTS input. Second, HDLC bus is a syn-
chronous digital open-drain connection for short-distance configurations, rather than the
more complex definition of the S/T interface. Third, HDLC bus allows any HDLC-based
frame protocol to be implemented at layer 2, not just LAPD. Fourth, HDLC bus devices wait
either 8 or 10 bit times before transmitting, rather than 7, 8, 9, or 10 bits (HDLC bus has one
"class" rather than two).
Figure 7-54 shows HDLC-bus in its most common LAN configuration. All stations may trans-
mit and receive data to/from every other station on the LAN. All transmissions are half-
duplex, as is typical in LANs.
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MC68360 USER’S MANUAL
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