MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 291

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Table 6-7 shows which combinations of A0-A1 and SIZ1-SIZ0, on eitherthe external bus or
the IMB bus, assert the BKPT pin.
NEG—Negative Breakpoint Match
MA1–MA0—Mask Address
AS8–AS0—Address Space Bits
This bit allows the breakpoint match to occur, using negative address matching logic,
when a block address is selected. If this bit is set, the rest of the address and address
match logic define when a breakpoint match is not to occur. The R/W, size, and FC com-
pare logic are not affected by the NEG bit.
The address mask bits allow the breakpoint logic to assert the breakpoint on a memory
block boundary.
The address space field allows particular address spaces (function code combinations) to
be masked during the breakpoint match decision. If an address space is masked, an ac-
cess to this space will NOT assert the BKPT pin. To ignore function codes in the break-
point match decision, program these bits to zero. The address space bits are:
AS8—Mask DMA space address space (FC3–FC0 = 1xxx)
AS7—Mask CPU space address space (FC3–FC0 = 0111)
AS6—Mask supervisor program address space (FC3–FC0 = 0110)
AS5—Mask supervisor data address space (FC3–FC0 = 0101)
AS4—Mask [Motorola reserved] address space (FC3–FC0 = 0100)
AS3—Mask [user reserved] address space (FC3–FC0 = 0011)
AS2—Mask user program address space (FC3–FC0 = 0010)
AS1—Mask user data address space (FC3–FC0 = 0001)
AS0—Mask [Motorola reserved] address space (FC3–FC0 = 0000)
0 = Assert a breakpoint when the memory cycle matches the programmed values.
1 = Assert a breakpoint when the memory cycle does not match the programmed block
00 = No address bits are masked, 32 address bits are compared.
01 = Mask address bits 10–0; the block size is 2K.
10 = Mask address bits 12–0; the block size is 8K.
11 = Mask address bits 14–0; the block size is 32K.
address. NEG is ignored if the MA bits are 00.
The table is true for the case SIZM=1.
Breakpoint will be asserted ONLY if the programmed address is
actually accessed.
Using the NEG bit, the breakpoint can be asserted for accesses
that fall into the block range or for those that fall out of the block
range.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE
System Integration Module (SIM60)