MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 486

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
CM—Continuous Mode
ID—Buffer Closed on Reception of Idles
AM—Address Match
BR—Break Received
FR—Framing Error
PR—Parity Error
OV—Overrun
CD—Carrier Detect lost
Data Length
7-162
The buffer was closed due to the reception of the programmable number of consecutive
idle sequences (defined in MAX_IDL).
This bit has meaning only if the address bit is set and the automatic multidrop mode was
selected in the UM bits. Following an address match, this bit defines which address char-
acter matched the user-defined address character, enabling the UART to receive data.
A break sequence was received while receiving data into this buffer.
A character with a framing error was received and is located in the last byte of this buffer.
A framing error is a character without a stop bit. A new receive buffer will be used for fur-
ther data reception.
A character with a parity error was received and is located in the last byte of this buffer. A
new receive buffer will be used for further data reception.
A receiver overrun occurred during message reception.
The carrier detect signal was negated during message reception.
Data length is the number of octets written by the CP into this BD’s data buffer. It is written
by the CP once as the BD is closed.
0 = Normal operation.
1 = The E-bit is not cleared by the CP after this BD is closed, allowing the associated
0 = The address matched the value in UADDR2.
1 = The address matched the value in UADDR1.
data buffer to be overwritten automatically when the CP next accesses this BD.
However, the E-bit will be cleared if an error occurs during reception, regardless of
the CM bit.
The actual amount of memory allocated for this buffer should be
greater than or equal to the contents of the MRBLR.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE