MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 519

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.10.18.2.4 Using the TSA. Sometimes HDLC bus may be used in a configuration that has
a local HDLC bus, and a TDM transmission line that is not an HDLC bus. Figure 7-60 shows
such a case. The local HDLC bus controllers all communicate over time slots; however,
more than one HDLC bus controller is assigned to a given time slot, and the HDLC bus pro-
tocol is used to control access during that time slot.
Once again, the local HDLC controllers do not communicate with each other, only with the
transmission line. If the SCC is configured to operate using the TSA of the SI, then the data
will be received and transmitted using the L1TXDx and L1RXDx pins. The collision sensing
TX
RX
NOTES:
1. All Tx pins of slave devices should be configured to open-drain in the port C parallel I/O port.
2. The TSA in the SI of each station is used to configure the desired time slot.
3. The choice of the number of stations to share a time slot is user-defined. It is two in this example.
TCLK
CTS
RTS
Figure 7-60. HDLC Bus TSA Transmission Line Configuration
TXD
DRIVER
LINE
Freescale Semiconductor, Inc.
For More Information On This Product,
CONTROLLER
HDLC BUS
Figure 7-59. Delayed RTS Mode
1ST BIT
STATIONS SHARE TIME SLOT N
A
CTS
MC68360 USER’S MANUAL
Go to: www.freescale.com
2ND BIT
CONTROLLER
HDLC BUS
B
CTS
COLLISION
3RD BIT
LOCAL HDLC BUS
Serial Communication Controllers (SCCs)
CONTROLLER
HDLC BUS
STATIONS SHARE TIME SLOT M
C
CTS
RTS ACTIVE FOR ONLY
2 BIT TIMES
CONTROLLER
HDLC BUS
D
CTS
R
+5