MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 447

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

All protocols can have their buffer descriptors point to data buffers that are located in internal
dual-port RAM. Typically, however, due to the internal RAM being used for buffer descrip-
tors, it is customary for the data buffers to be located in external RAM, especially if the data
buffers are large in size. In all cases, the IMB is used to transfer the data to the data buffer.
The CP processes the Tx BDs in a straightforward fashion. Once the transmit side of an
SCC is enabled, it starts with the first BD in that SCC’s transmit table. Once the CP detects
that the Tx BD R-bit was set, it will begin processing the buffer. (The CP will detect that the
BD is ready either by polling the R-bit periodically or by the user writing to the transmit-on-
demand register (TODR).) Once the data from the BD has been placed in the transmit FIFO,
the CP moves on to the next BD, again waiting for that BD’s R-bit to be set. Thus, the CP
does no look-ahead BD processing, nor does it skip over BDs that are not ready. When the
CP sees the wrap (W) bit set in a BD, it goes back to the beginning of the BD table after
processing of the BD is complete. After using a BD, the CP normally sets the R-bit to not-
DUAL-PORT RAM
TABLE POINTER
TABLE POINTER
SCC1 RX BD
SCC1 RX BD
SCC1 TX BD
SCC1 TX BD
TABLE
TABLE
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 7-38. SCC Memory Structure
MC68360 USER’S MANUAL
Go to: www.freescale.com
FRAME STATUS
DATA LENGTH
DATA POINTER
FRAME STATUS
DATA LENGTH
DATA POINTER
TX BUFFER DESCRIPTORS
RX BUFFER DESCRIPTORS
Serial Communication Controllers (SCCs)
EXTERNAL MEMORY
RX DATA BUFFER
TX DATA BUFFER