MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 675

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Certain parameter RAM values above (marked in bold face) need to be initialized by the
user before the PIP is enabled; the others are initialized/written by the CP. Once initialized,
most parameter RAM values will not need to be accessed in user software since most of the
activity is centered around the transmit buffer descriptors, not the parameter RAM.
7.13.8.14 BUFFER DESCRIPTOR TABLE POINTER (RBASE). The RBASE entry defines
the starting location in the dual-port RAM for the PIP receiver’s set of buffer descriptors. This
provides a great deal of flexibility in how BDs are partitioned. By programming the RBASE
entry and by setting the "wrap" bit in the last BD, the user may select how many BDs to allo-
cate for the receive function. The user must initialize RBASE before enabling the channel.
7.13.8.15 CENTRONICS FUNCTION CODE REGISTER (CFCR). The FC entry contains
the value that the user would like to appear on the function code pins (FC3-0) when the
associated SDMA channel accesses memory. It also controls the byte ordering convention
to be used in the transfers.
PIP Base+12
PIP Base+14
PIP Base+18
PIP Base+1C
PIP Base+20
PIP Base+22
PIP Base+24
PIP Base+28
PIP Base+2a
PIP Base+2c
PIP Base+2E
PIP Base+30
PIP Base+32
PIP Base+34
PIP Base+36
PIP Base+38
PIP Base+3A
PIP Base+3C
PIP Base+3E
Address
.RBASE should contain a value that is divisible by 8.
Table 7-18. Centronics Receiver Parameter RAM
R_CNT
RTEMP
Res
Res
Res
Res
Res
MAX_SL
SL_CNT
CHARCTER1
CHARCTER2
CHARCTER3
CHARCTER4
CHARCTER5
CHARCTER6
CHARCTER7
CHARCTER8
RCCM
RCCR
Freescale Semiconductor, Inc.
For More Information On This Product,
Name
MC68360 USER’S MANUAL
Go to: www.freescale.com
Word
Long
Word
Word
Word
Word
Long
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Width
NOTE
Rx Internal Byte Count
Rx Temp
Reserved
Reserved
Reserved
Reserved
Reserved
Maximum Silence period
Silence counter
CONTROL character 1
CONTROL character 2
CONTROL character 3
CONTROL character 4
CONTROL character 5
CONTROL character 6
CONTROL character 7
CONTROL character 8
Receive Control Character Mask
Receive Character Control Register
Description
Parallel Interface Port (PIP)