MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 208

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
“not ready/come again” response. Once the receive data latch has been loaded, the CPU is
released to act on the new data. Response data overwrites the “not ready” response when
the CPU has completed the current operation.
Data written into the output shift register appears immediately on the DSO signal. In general,
this action changes the state of the signal from a high (“not ready” response status bit) to a
low (valid data status bit) logic level. However, this level change only occurs if the command
completes successfully. Error conditions overwrite the “not ready” response with the appro-
priate response that also has the status bit set.
A user can use the state change on DSO to signal hardware that the next serial transfer may
begin. A timeout of sufficient length to trap error conditions that do not change the state of
DSO should also be incorporated into the design. Hardware interlocks in the CPU prevent
result data from corrupting serial transfers in progress.
5.6.2.7.2 Development System Serial Logic. The development system, as the master of
the serial data link, must supply the serial clock. However, normal and BDM operations
could interact if the clock generator is not properly designed.
Breakpoint requests are made by asserting BKPT to the low state in either of two ways. The
primary method is to assert BKPT during a single bus cycle for which an exception is
desired. Another method is to assert BKPT, then continue to assert it until the CPU32+
responds by asserting FREEZE. This method is useful for forcing a transition into BDM when
5-66
SYNCHRONIZED
SYNCHRONIZED
INTERNAL
INTERNAL
WINDOW
SAMPLE
CLKOUT
CLKOUT
FREEZE
DSCLK
DSCLK
DSO
Figure 5-23. Serial InterfaceTiming Diagram
DSI
DSI
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com