MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 680

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Parallel I/O Ports
CHR—Character Received
RX—Rx Buffer
7.13.9 Port B Registers
The PIP is associated with parallel I/O port B. The basic operation of the port is shown in
Figure 7-96. The registers are described in the port B description; however, the registers as
they relate to the PIP are mentioned in the following paragraphs.
7.13.9.1 PORT B ASSIGNMENT REGISTERS (PBPAR). The PBPAR is an 18-bit, mem-
ory-mapped, read-write register. To use port B pins as PIP pins, the corresponding PBPAR
bits MUST BE CLEARED, and the MODH and MODL bits in the PIP configuration register
may be configured as desired.
7.13.9.2 DATA DIRECTION REGISTER (PBDIR). The PBDIR is an 18-bit, memory-
mapped, read-write register. The description of PBDIR in 7.14.7 Port B Registers is also
valid for the PIP.
7.13.9.3 DATA REGISTER (PBDAT). PBDAT functions as the PIP data register when the
PIP is operational. This register is used to receive/transmit PIP data when the PIP is under
host software control. The description of PBDAT in 7.14.7 Port B Registers is also valid for
the PIP.
7.13.9.4 OPEN-DRAIN REGISTER (PBODR). The description of PBODR in 7.14.7 Port B
Registers is also valid for the PIP.
7.14 PARALLEL I/O PORTS
The CPM supports three general-purpose I/O ports: A, B, and C.
7-356
A character was received from the Centronics channel and was written to the receive buff-
er.
A buffer has been received on the Centronics channel.
READ FROM IMB
WRITE FROM IMB
Figure 7-96. Port B General-Purpose I/O
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
BUFFER
LATCH
Go to: www.freescale.com
DIR = OUTPUT
I/O
PIN