MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 229

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The number of cycles for the instruction (C
tion to the raw number in the cycles column. In these cases, calculate overall instruction time
as if it were for multiple instructions, using the following equation:
where:
The overall head for the instruction is the head for the EA, and the overall tail for the instruc-
tion is the tail for the operation. Therefore, the actual equation for execution time becomes:
C
Every instruction must prefetch to replace itself in the instruction pipe. Usually, these
prefetches occur during or after an instruction. A prefetch is permitted to begin in the first
clock of any indexed EA mode operation.
Additionally, a prefetch for an instruction is permitted to begin two clocks before the end of
an instruction provided the bus is not being used. If the bus is being used, then the prefetch
occurs at the next available time when the bus would otherwise be idle.
5.7.1.7 EFFECTS OF NEGATIVE TAILS. When the CPU32+ changes instruction flow, the
instruction decode pipeline must begin refilling before instruction execution can resume.
Refilling forces a two-clock idle period at the end of the change-of-flow instruction. This idle
period can be used to prefetch an additional word on the new instruction path. Because of
the stipulation that each instruction must prefetch to replace itself, the concept of negative
tails has been introduced to account for these free clocks on the bus.
On a two-clock bus, it is not necessary to adjust instruction timing to account for the potential
extra prefetch. The cycle times of the microsequencer and bus are matched, and no addi-
tional benefit or penalty is obtained. In the instruction execution time equations, a zero
should be used instead of a negative number.
Negative tails are used to adjust for slower fetches on slower buses. Normally, increasing
the length of prefetch bus cycles directly affects the cycle count and tail values found in the
tables.
CEA
op1
T
H
min (T
C
T
H
min (T
CEA is the instruction’s EA time
N
ea
N
op
op
is the tail time for instruction N
is the head time for instruction N
is the EA’s tail time
is the instruction’s operation time
is the instruction operation’s head time
min (T
N
min (T
n
, H
, H
m
M
op1
) is the minimum of parameters T
) is the minimum of parameters T
ea
, H
, H
ea2
op
)
)
Freescale Semiconductor, Inc.
C
For More Information On This Product,
CEA
op
2
MC68360 USER’S MANUAL
Go to: www.freescale.com
min (T
N
ea2
) can include one or two EA calculations in addi-
, H
n
N
op2
and H
and H
)
C
m
M
op2
min (T
op2
, H
ea3
)
CPU32+