MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 10

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Table of Contents
Paragraph
Number
5.5.4.1
5.5.4.2
5.5.4.3
5.6
5.6.1
5.6.1.1
5.6.1.2
5.6.1.3
5.6.2
5.6.2.1
5.6.2.2
5.6.2.2.1
5.6.2.2.2
5.6.2.2.3
5.6.2.3
5.6.2.4
5.6.2.5
5.6.2.5.1
5.6.2.5.2
5.6.2.5.3
5.6.2.6
5.6.2.7
5.6.2.7.1
5.6.2.7.2
5.6.2.8
5.6.2.8.1
5.6.2.8.2
5.6.2.8.3
5.6.2.8.4
5.6.2.8.5
5.6.2.8.6
5.6.2.8.7
5.6.2.8.8
5.6.2.8.9
5.6.2.8.10
5.6.2.8.11
5.6.2.8.12
5.6.2.8.13
5.6.2.8.14
5.6.2.8.15
5.6.2.8.16
5.6.3
5.6.3.1
5.6.3.2
5.6.3.3
vi
Four-Word Stack Frame ........................................................................5-56
Six-Word Stack Frame...........................................................................5-56
Bus Error Stack Frame ..........................................................................5-56
Development Support ............................................................................5-59
CPU32+ Integrated Development Support ............................................5-59
Background Debug Mode (BDM) Overview...........................................5-59
Deterministic Opcode Tracking Overview..............................................5-60
On-Chip Hardware Breakpoint Overview...............................................5-60
Background Debug Mode ......................................................................5-60
Enabling BDM ........................................................................................5-60
BDM Sources.........................................................................................5-61
External BKPT Signal ............................................................................5-62
BGND Instruction ...................................................................................5-62
Double Bus Fault ...................................................................................5-62
Entering BDM.........................................................................................5-62
Command Execution..............................................................................5-62
BDM Registers.......................................................................................5-63
Fault Address Register (FAR)................................................................5-63
Return Program Counter (RPC).............................................................5-63
Current Instruction Program Counter (PCC)..........................................5-63
Returning from BDM ..............................................................................5-63
Serial Interface.......................................................................................5-63
CPU Serial Logic....................................................................................5-65
Development System Serial Logic .........................................................5-66
Command Set ........................................................................................5-68
Command Format ..................................................................................5-68
Command Sequence Diagram...............................................................5-69
Command Set Summary........................................................................5-69
Read A/D Register (RAREG/RDREG)...................................................5-71
Write A/D Register (WAREG/WDREG) .................................................5-71
Read System Register (RSREG)...........................................................5-71
Write System Register (WSREG) ..........................................................5-72
Read Memory Location (READ) ............................................................5-73
Write Memory Location (WRITE) ...........................................................5-74
Dump Memory Block (DUMP)................................................................5-75
Fill Memory Block (FILL) ........................................................................5-76
Resume Execution (GO)........................................................................5-77
Call User Code (CALL) ..........................................................................5-77
Reset Peripherals (RST)........................................................................5-79
No Operation (NOP) ..............................................................................5-79
Future Commands .................................................................................5-80
Deterministic Opcode Tracking..............................................................5-80
Instruction Fetch (IFETCH) ....................................................................5-80
Instruction Pipe (IPIPE1–IPIPE0) ..........................................................5-80
Opcode Tracking during Loop Mode......................................................5-82
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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