MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 231

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

accesses, add two clocks to the tail and to the number of cycles (“X” in table notation) to
obtain head = 4, tail = 4, cycles = 10 (2/1/0).
Assuming that no trailing write exists from the previous instruction, EA calculation requires
six clocks. Replacement fetch for the EA occurs during these six clocks, leaving a head of
four. If there is no time in the head to perform a prefetch due to a previous trailing write, then
additional time to perform the prefetches must be allotted in the middle of the instruction or
after the tail.
The total number of clocks for bus activity is as follows:
(2 Reads
(0 Writes
The number of internal clocks (not overlapped by bus activity) is as follows:
10 Clocks Total
Memory read requires two bus cycles at two clocks each. This read time, implied in the tail
figure for the EA, cannot be overlapped with the instruction because the instruction has a
head of zero. An additional two clocks are required for the ADD instruction itself. The total
is 6
appropriate number of clocks to each memory access.
The instruction sequence MOVE.L D0, (A0) followed by LSL.L #7, D2 provides an example
of overlapped execution. The MOVE instruction has a head of zero and a tail of four because
it is a long write. The LSL instruction has a head of four. The trailing write from the MOVE
overlaps the LSL head completely. Thus, the two-instruction sequence has a head of zero,
a tail of zero, and a total execution of 8 rather than 12 clocks.
General observations regarding calculation of execution time are as follows:
• Any time the number of bus cycles is listed as "X", substitute a value of one for byte and
• The time calculated for an instruction on a three-clock (or longer) bus is usually longer
• If the previous instruction has a negative tail, then a prefetch for the current instruction
• Certain instructions requiring an immediate extension word (immediate word EA, abso-
word cycles and a value of two for long cycles. For long bus cycles, usually add a value
of two to the tail.
than the actual execution time. All times shown are for two-clock bus cycles.
can begin during the execution of that previous instruction.
lute word EA, address register indirect with displacement EA, conditional branches with
word offsets, bit operations, LPSTOP, TBL, MOVEM, MOVEC, MOVES, MOVEP,
4
2 = 12 clocks. If bus cycles take more time (i.e., the memory is off-chip), add an
2 Clocks/Write) = 6 Clocks of Bus Activity
2 Clocks/Read)
6 Clocks Bus Activity = 4 Internal Clocks
Freescale Semiconductor, Inc.
NUMBER OF INSTRUCTION ACCESS CYCLES
For More Information On This Product,
(1 Instruction Access
MC68360 USER’S MANUAL
Go to: www.freescale.com
TOTAL NUMBER OF CLOCKS
NUMBER OF WRITE CYCLES
NUMBER OF READ CYCLES
2 Clocks/Access)
8 (2 /1 /0)
CPU32+