MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 19

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.10.20.9
7.10.20.10
7.10.20.10.1 Transmission Errors ............................................................................ 7-209
7.10.20.10.2 Reception Errors ................................................................................. 7-209
7.10.20.11
7.10.20.12
7.10.20.13
7.10.20.14
7.10.20.15
7.10.20.16
7.10.20.17
7.10.20.18
7.10.21
7.10.21.1
7.10.21.2
7.10.21.3
7.10.21.4
7.10.21.4.1 In-Line Synchronization Pattern .......................................................... 7-223
7.10.21.4.2 Transparent Synchronization Example ............................................... 7-224
7.10.21.5
7.10.21.6
7.10.21.6.1 Transmit Commands ........................................................................... 7-226
7.10.21.6.2 Receive Commands ............................................................................ 7-227
7.10.21.7
7.10.21.7.1 Transmission Errors ............................................................................ 7-227
7.10.21.7.2 Reception Errors ................................................................................. 7-228
7.10.21.8
7.10.21.9
7.10.21.10
7.10.21.11
7.10.21.12
7.10.21.13
7.10.21.14
7.10.22
7.10.23
7.10.23.1
7.10.23.2
7.10.23.3
7.10.23.4
7.10.23.5
7.10.23.6
7.10.23.7
7.10.23.8
7.10.23.9
7.10.23.10
Paragraph
Number
Transmitting and Receiving the Synchronization Sequence ............... 7-208
BISYNC Error-Handling PROCEDURE............................................... 7-209
BISYNC Mode Register (PSMR)......................................................... 7-209
BISYNC Receive Buffer Descriptor (Rx BD) ....................................... 7-211
BISYNC Transmit Buffer Descriptor (Tx BD)....................................... 7-213
BISYNC Event Register (SCCE) ......................................................... 7-216
BISYNC Mask Register (SCCM) ......................................................... 7-217
SCC Status Register (SCCS).............................................................. 7-217
Programming the BISYNC Controller.................................................. 7-217
SCC BISYNC Example ....................................................................... 7-218
Transparent Controller ........................................................................ 7-220
Transparent Controller Features ......................................................... 7-221
Transparent Channel Frame Transmission Processing ...................... 7-221
Transparent Channel Frame Reception Processing ........................... 7-222
Achieving Synchronization in Transparent Mode ................................ 7-223
Transparent Memory Map ................................................................... 7-225
Transparent Command Set ................................................................. 7-226
Transparent Error-Handling Procedure ............................................... 7-227
Transparent Mode Register (PSMR)................................................... 7-228
Transparent Receive Buffer Descriptor (Rx BD) ................................. 7-228
Transparent Transmit Buffer Descriptor (Tx BD)................................. 7-230
Transparent Event Register (SCCE) ................................................... 7-232
Transparent Mask Register (SCCM) ................................................... 7-233
SCC Status Register (SCCS).............................................................. 7-233
SCC Transparent Example ................................................................. 7-233
RAM Microcodes ................................................................................. 7-235
Ethernet Controller .............................................................................. 7-235
Ethernet On QUICC—MC68EN360 .................................................... 7-236
Ethernet Key Features ........................................................................ 7-237
Learning Ethernet on the QUICC ........................................................ 7-238
Connecting QUICC to Ethernet ........................................................... 7-239
Ethernet Channel Frame Transmission............................................... 7-241
Ethernet Channel Frame Reception.................................................... 7-242
CAM Interface ..................................................................................... 7-243
Ethernet Memory Map......................................................................... 7-246
Ethernet Programming Model ............................................................. 7-250
Ethernet Command Set....................................................................... 7-250
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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