MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 479
![IC MPU QUICC 25MHZ 240-FQFP](/photos/39/60/396094/4532975_sml.jpg)
MC68EN360CAI25L
Manufacturer Part Number
MC68EN360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Series
MC68000r
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360CAI25L.pdf
(962 pages)
Specifications of MC68EN360CAI25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Core Size
32 Bit
Cpu Speed
25MHz
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
No. Of Pins
240
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360CAI25L
Manufacturer:
APLHA
Quantity:
12 000
Company:
Part Number:
MC68EN360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EN360CAI25L
Manufacturer:
FREESCALE
Quantity:
20 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360CAI25L PDF datasheet #4
- Current page: 479 of 962
- Download datasheet (4Mb)
and the UART event register. The modem interface lines can be monitored by the port C
pins.
7.10.16.14.1 Transmission Error. The following paragraph describes a UART transmis-
sion error.
CTS Lost During Character Transmission . When this error occurs, the channel stops trans-
mission after finishing transmission of the current character from the buffer. The channel
then sets the CT bit in the Tx BD and generates the TX interrupt if it is not masked. The chan-
nel will resume transmission after the RESTART TRANSMIT command is issued and the
CTS pin is asserted.
7.10.16.14.2 Reception Errors. The following paragraphs describe various types of UART
reception errors.
Overrun Error . Data is moved from the receive FIFO to the data buffer when the first byte is
received into the FIFO. If a receiver FIFO overrun occurs, the channel writes the received
character into the internal FIFO over the previous received character (previous character is
lost.) The channel writes the received character to the buffer, closes the buffer, sets the OV
bit in the Rx BD, and generates the RX interrupt if it is enabled. In automatic multidrop mode,
the receiver enters hunt mode immediately.
CD Lost During Character Reception . If this error occurs and the channel is using this pin to
automatically control reception, the channel terminates character reception, closes the
buffer, sets the CD bit in the Rx BD, and generates the RX interrupt (if enabled). This error
has the highest priority. The last character in the buffer is lost, and other errors are not
checked. In automatic multidrop mode, the receiver enters hunt mode immediately.
Parity Error . When a parity error occurs, the channel writes the received character to the
buffer, closes the buffer, sets the PR bit in the Rx BD, and generates the RX interrupt (if
enabled). The channel also increments the PAREC counter. In automatic multidrop mode,
the receiver enters hunt mode immediately.
Noise Error . Noise error is detected by the UART controller when the three samples taken
on every bit are not identical. When this error occurs, the channel writes the received char-
acter to the buffer and proceeds normally, but increments the NOSEC.
Idle Sequence Receive . An idle is detected when one character consisting of all ones is
received. When the UART is receiving data into a receive buffer, and an idle is received, the
The UART also offers an asynchronous flow control option using
CTS that does not generate an error. See the FLC bit in the
PSMR description.
In the synchronous mode of the UART controller, this error can-
not occur.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE
Serial Communication Controllers (SCCs)
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