MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 555

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

W—Wrap (Final BD in Table)
I—Interrupt
L—Last in Message
TC—Transmit CRC
CM—Continuous Mode
UN—Underrun
CT—CTS Lost
Data Length
Tx Data Buffer Pointer
The SCC encountered a transmitter underrun condition while transmitting the associated
data buffer.
CTS was lost during frame transmission.
The data length is the number of bytes that the CP should transmit from this BD’s data
buffer. The data length, which should be greater than zero, may be even or odd. This val-
ue is never modified by the CP.
The transmit buffer pointer, which always points to the first byte of the associated data
buffer, may be even or odd. The buffer may reside in either internal or external memory.
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the Tx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been serviced.
1 = When this buffer is serviced by the CP, TX, or TXE bit in the transparent event reg-
0 = The last byte in the buffer is not the last byte in the transmitted transparent frame.
1 = The last byte in the buffer is the last byte in the transmitted transparent frame. After
0 = No CRC sequence will be transmitted after this buffer.
1 = A frame check sequence as defined by the TCRC bits in the GSMR will be trans-
0 = Normal operation.
1 = The R-bit is not cleared by the CP after this BD is closed, allowing the associated
receive incoming data into the first BD in the table (the BD pointed to by TBASE).
The number of Tx BDs in this table is programmable, and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
ister will be set. The TX and TXE bits can cause interrupts if they are enabled.
Data from the next transmit buffer (if ready) will be transmitted immediately follow-
ing the last byte of this buffer.
this buffer is transmitted, the transmitter will require synchronization before the
next buffer will be transmitted.
mitted after the last byte of this buffer.
data buffer to be retransmitted automatically when the CP next accesses this BD.
However, the R-bit will be cleared if an error occurs during transmission, regard-
less of the CM bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)