MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 216

IC MPU QUICC 25MHZ 240-FQFP

MC68EN360CAI25L

Manufacturer Part Number
MC68EN360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Series
MC68000r

Specifications of MC68EN360CAI25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Core Size
32 Bit
Cpu Speed
25MHz
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
No. Of Pins
240
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EN360CAI25L
Manufacturer:
APLHA
Quantity:
12 000
Part Number:
MC68EN360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EN360CAI25L
Manufacturer:
FREESCALE
Quantity:
20 000
CPU32+
Result Data:
5.6.2.8.9 Write Memory Location (WRITE). Write the operand data to the memory loca-
tion specified by the long-word address. The DFC register determines the address space
accessed. Only absolute addressing is supported. Valid data sizes include byte, word, and
long word.
Command Format:
Command Sequence:
Operand Data:
5-74
15
The requested data is returned as either a word or long word. Byte data is returned in the
least significant byte of a word result, with the upper byte cleared. Word results return 16
bits of significant data; long-word results return 32 bits.
A successful read operation returns data bit 16 cleared. If a bus or address error is en-
countered, the returned data is $10001.
Two operands are required for this instruction. The first operand is a long-word absolute
address that specifies a location to which the operand data is to be written. The second
operand is the data. Byte data is transmitted as a 16-bit word, justified in the least signif-
icant byte; 16- and 32-bit operands are transmitted as 16 and 32 bits, respectively.
0
WRITE (B/W)
WRITE (LONG)
14
???
0
???
13
0
12
1
"NOT READY"
"NOT READY"
"ILLEGAL"
MS ADDR
MS ADDR
"ILLEGAL"
XXX
XXX
11
Freescale Semiconductor, Inc.
1
For More Information On This Product,
10
0
"NOT READY"
"NOT READY"
MC68360 USER’S MANUAL
NEXT CMD
"NOT READY"
"NOT READY"
LS ADDR
Go to: www.freescale.com
NEXT CMD
LS ADDR
0
9
8
0
"NOT READY"
"NOT READY"
LS DATA
"NOT READY"
DATA
MS DATA
7
OP SIZE
6
LOCATION
MEMORY
LOCATION
MEMORY
WRITE
WRITE
5
0
4
0
3
0
"NOT READY"
"CMD COMPLETE"
"CMD COMPLETE"
"NOT READY"
BERR/AERR
BERR/AERR
NEXT CMD
NEXT CMD
XXX
XXX
XXX
XXX
XXX
2
0
XXX
"NOT READY"
NEXT CMD
"NOT READY"
NEXT CMD
1
0
0
0

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