MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 626

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Management Controllers (SMCs)
UN—Underrun
Data Length
Tx Data Buffer Pointer
7.11.10.13 SMC TRANSPARENT EVENT REGISTER (SMCE). SMCE is referred to as the
SMC transparent event register when the SMC is programmed for transparent mode. It is
an 8-bit register used to report events recognized by the SMC channel and to generate inter-
rupts. On recognition of an event, the SMC controller sets the corresponding bit in the
SMCE. Interrupts generated by this register may be masked in the SMC mask register.
The SMCE is a memory-mapped register that may be read at any time. A bit is cleared by
writing a one (writing a zero does not affect a bit’s value). More than one bit may be cleared
at a time. All unmasked bits must be cleared before the CP will clear the internal interrupt
request. This register is cleared at reset.
Bits 7–5, 3—Reserved
TXE—Tx Error
BSY—Busy Condition
TX—Tx Buffer
7-302
The SMC encountered a transmitter underrun condition while transmitting the associated
data buffer.
The data length is the number of octets that the CP should transmit from this BD’s data
buffer. This value is never modified by the CP.
The data length may be even or odd; however, if the number of bits in the transparent
character is greater than 8, the data length should be even. Example: to transmit three
transparent 8-bit characters, the data length field should be initialized to 3. However, to
transmit three transparent 9-bit characters, the data length field should be initialized to 6,
since the three 9-bit characters occupy three words in memory (the 9 LSBs of each word).
The transmit buffer pointer, which always points to the first byte of the associated data
buffer, may be even or odd (unless the character length is greater than 8 bits, in which
case the transmit buffer pointer must be even). For instance, the pointer to 8-bit transpar-
ent characters may be even or odd, but the pointer to 9-bit transparent characters must
be even. The buffer may reside in either internal or external memory.
An underrun error occurred on the transmitter channel.
A character was received and discarded due to lack of buffers. Reception will begin after
a new buffer is provided. The user may wish to execute an ENTER HUNT MODE com-
mand to cause the receiver to wait for re-synchronization.
A buffer has been transmitted. If the L-bit of the Tx BD is set, this bit is set when the last
data character begins to be transmitted; the user must wait one character time to be sure
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Freescale Semiconductor, Inc.
7
For More Information On This Product,
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6
MC68360 USER’S MANUAL
Go to: www.freescale.com
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5
TXE
4
—
3
BSY
2
TX
1
RX
0