MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 506

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
CM—Continuous Mode
DE—DPLL Error
LG—Rx Frame Length Violation
NO—Rx Nonoctet Aligned Frame
AB—Rx Abort Sequence
CR—Rx CRC Error
OV—Overrun
CD—Carrier Detect Lost
Data Length
7-182
This bit is set by the HDLC controller when a DPLL error has occurred during the reception
of this buffer. In decoding modes where a transition is promised every bit, the DE bit will
be set when a missing transition has occurred.
A frame length greater than the maximum defined for this channel was recognized (only
the maximum-allowed number of bytes (MFLR) is written to the data buffer). This event
will not be reported until the Rx BD is closed and the RXF bit is set, after receipt of the
closing flag. The actual number of bytes received between flags is written to the data
length field of this BD.
A frame that contained a number of bits not exactly divisible by eight was received.
A minimum of seven consecutive ones was received during frame reception.
This frame contains a CRC error. The received CRC bytes are always written to the re-
ceive buffer.
A receiver overrun occurred during frame reception.
The carrier detect signal was negated during frame reception. This bit is only valid when
working in the NMSI mode.
Data length is the number of octets written by the CP into this BD’s data buffer. It is written
by the CP once as the BD is closed.
When this BD is the last BD in the frame (L = 1), the data length contains the total number
of frame octets (including 2 or 4 bytes for CRC).
The actual amount of memory allocated for this buffer should be greater than or equal to
the contents of the MRBLR.
0 = Normal operation.
1 = The E-bit is not cleared by the CP after this BD is closed, allowing the associated
data buffer to be overwritten automatically when the CP next accesses this BD.
However, the E-bit will be cleared if an error occurs during reception, regardless of
the CM bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com