MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 445
![IC MPU QUICC 25MHZ 240-FQFP](/photos/39/60/396094/4532975_sml.jpg)
MC68EN360CAI25L
Manufacturer Part Number
MC68EN360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Series
MC68000r
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360CAI25L.pdf
(962 pages)
Specifications of MC68EN360CAI25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Core Size
32 Bit
Cpu Speed
25MHz
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
No. Of Pins
240
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360CAI25L
Manufacturer:
APLHA
Quantity:
12 000
Company:
Part Number:
MC68EN360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EN360CAI25L
Manufacturer:
FREESCALE
Quantity:
20 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360CAI25L PDF datasheet #4
- Current page: 445 of 962
- Download datasheet (4Mb)
7.10.4 SCC Data Synchronization Register (DSR)
Each of the four SCC has a 16-bit, memory-mapped, read-write DSR. The DSR specifies
the pattern used in the frame synchronization procedure in the synchronous protocols. In
the UART protocol, it is used to configure fractional stop bit transmission. In the BISYNC and
totally transparent protocol, it should be programmed with the desired SYNC pattern. In the
Ethernet protocol, it should be programmed with $D555. At reset, it defaults to $7E7E (two
HDLC flags), so it does not need to be written for HDLC mode. When DSR is used to send
out SYNCs (such as in BISYNC or transparent mode), the contents of the DSR are always
transmitted LSB first.
7.10.5 SCC Transmit on Demand Register (TODR)
If no frame is currently being transmitted by an SCC, the RISC controller periodically polls
the R-bit of the next Tx BD to see if the user has requested a new frame/buffer to be trans-
mitted. This polling algorithm depends on the SCC configuration, but occurs every 8 to 32
serial transmit clocks. The user, however, has an option to request that the RISC begin the
processing of the new frame/buffer immediately, without waiting until the normal polling
time. To obtain immediate processing, the TOD bit in the transmit-on-demand register is set
by the user once the user has set the R-bit in the Tx BD.
This feature, which decreases the transmission latency of the transmit buffer/frame, is par-
ticularly useful in LAN-type protocols where maximum interframe GAP times are limited by
the protocol specification. Since the transmit-on-demand feature gives a high priority to the
specified Tx BD, it can conceivably affect the servicing of the other SCC FIFOs. Therefore,
it is recommended that the transmit-on-demand feature only be used when a high-priority
Tx BD has been prepared and transmission on this SCC has not occurred for a period of
time.
The TOD bit does not need to be set if a new Tx BD is added to the circular queue but other
Tx BDs in that queue have not fully completed transmission. In that case, the new Tx BD will
be processed immediately following the completion of the older Tx BD s.
The first bit of the frame will typically be clocked out 5-6 bit times after TOD has been written
to a 1.
TOD—Transmit on Demand
TOD
15
15
0 = Normal operation
1 = The RISC will give a high priority to the current Tx BD and will not wait for the nor-
14
14
mal polling time to check that the Tx BD’s R-bit has been set. It will begin transmit-
ting the frame. This bit will be cleared automaticaly after one serial clock.
13
13
12
12
SYN2
Freescale Semiconductor, Inc.
11
11
For More Information On This Product,
10
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
9
9
8
8
—
7
7
Serial Communication Controllers (SCCs)
6
6
5
5
4
4
SYN1
3
3
2
2
1
1
0
0
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