MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 644

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Peripheral Interface (SPI)
7.12.5.2 SPI COMMAND REGISTER (SPCOM). The SPCOM is an 8-bit read-write register
that is used to start SPI operation.
Bits 6–0—Reserved.
STR—Start Transmit
7.12.5.3 SPI PARAMETER RAM MEMORY MAP. The SPI parameter RAM area (see
Table 7-16) begins at the SPI base address. This area is used for the general SPI parame-
ters. The user will notice that it is similar to the SCC general-purpose parameter RAM.
Certain parameter RAM values (marked in boldface) need to be initialized by the user before
the SPI is enabled; other values are initialized by the CP. Once initialized, the parameter
7-320
These bits should be written with zeros by the user.
When the SPI is configured as a master, setting the STR bit to one causes the SPI con-
troller to start the transmission and reception of data from/to the SPI transmit/receive buff-
ers (if they are configured as ready by the user).
When the SPI is configured as a slave, setting the STR bit to one when the SPI is idle
(between transfers) causes the SPI to load the transmit data register from the SPI transmit
buffer and start transmission as soon as the next SPI input clocks and select signal are
received.
The STR bit is cleared automatically after one system clock cycle.
NOTE: The items in boldface should be initialized by the user.
SPI Base + 00
SPI Base+ 02
SPI Base+ 04
SPI Base+ 05
SPI Base+ 06
SPI Base+ 08
SPI Base+ 0C
SPI Base+ 10
SPI Base+ 12
SPI Base+ 14
SPI Base+ 18
SPI Base+ 1C
SPI Base+ 20
SPI Base+ 22
SPI Base+ 24
Address
Table 7-16. SPI Parameter RAM Memory Map
STR
Freescale Semiconductor, Inc.
7
For More Information On This Product,
RSTATE
TSTATE
MRBLR
RBASE
TBASE
RBPTR
TBPTR
RFCR
Name
TFCR
6
MC68360 USER’S MANUAL
Go to: www.freescale.com
5
Width
Word
Word
Word
Word
Word
Word
Word
Long
Long
Long
Long
Long
Long
Byte
Byte
4
RESERVED
Rx BD Base Address
Tx BD Base Address
Rx Function Code
Tx Function Code
Maximum Receive Buffer Length
Rx Internal State
Rx Internal Data Pointer
Rx BD Pointer
Rx Temp
Tx Internal State
Tx Internal Data Pointer
Tx BD Pointer
Tx Internal Byte Count
Tx Temp
3
Rx Internal Byte Count
2
Description
1
0