MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 210

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the
assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32+ as the first
DSCLK.
DSCLK, the gated serial clock, is normally high, but it pulses low for each bit to be trans-
ferred. At the end of the seventeenth clock period, it remains high until the start of the next
transmission. Clock frequency is implementation dependent and may range from DC to the
maximum specified frequency. Although performance considerations might dictate a hard-
ware implementation, software solutions can be used provided serial bus timing is main-
tained.
5.6.2.8 COMMAND SET. The following paragraphs describe the command set available in
BDM.
5.6.2.8.1 Command Format. The following standard bit .command format is utilized by all
BDM commands.
Bits 15–10—Operation Field
R/W Field
Operand Size
Address/Data (A/D) Field
5-68
15
The operation field specifies the commands. This 6-bit field provides for a maximum of 64
unique commands.
The R/W field specifies the direction of operand transfer. When the bit is set, the transfer
is from theCPU to the development system. When the bit is cleared, data is written to the
CPU or to memory from the development system.
For sized operations, this field specifies the operand data size. All addresses are ex-
pressed as 32-bit absolute values. The size field is encoded as listed in Table 5-22..
The A/D field is used by commands that operate on address and data registers. It deter-
mines whether the register field specifies a data or address register. One indicates an ad-
dress register; zero indicates a data register. For other commands, this field may be
interpreted differently.
OPERATION
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-22. Size Field Encoding
Encoding
10
00
01
10
11
MC68360 USER’S MANUAL
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9
0
EXTENSION WORD(S)
R/W
8
7
OP SIZE
Operand Size
Reserved
6
Word
Long
Byte
5
0
4
0
A/D
3
2
REGISTER
0