MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 476

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
Transmission of out-of-sequence characters is also supported by the UART and is normally
used for the transmission of flow control characters such as XON or XOFF. This procedure
is performed using the TOSEQ entry in the UART parameter RAM.
The UART will poll TOSEQ whenever the transmitter is enabled for UART operation. This
includes during UART freeze operation, during UART buffer transmission, and when no
buffer is ready for transmission. The TOSEQ character is transmitted at a higher priority than
the other characters in the transmit buffer (if any), but does not preempt characters already
in the transmit FIFO. This means that the XON or XOFF character may not be transmitted
for eight character times (SCC1) or four character times (SCC2, SCC3, and SCC4). To
reduce this latency, the TFL bit in the GSMR should be set to decrease the FIFO size to one
character prior to enabling the SCC transmitter.
Bits 15–14—Don't Care. May be written with ones or zeros.
REA—Ready
I—Interrupt
CT—Clear-to-Send Lost
7-152
15
—
The fact that these bits are don’t cares allows full compatibility between TOSEQ on the
QUICC and CHARACTER8 on the MC68302.
This bit is set by the CPU32+ core when the character is ready for transmission and will
remain one while the character is being transmitted. The CP clears this bit after transmis-
sion.
If set, the CPU32+ core will be interrupted when this character has been transmitted. (The
TX bit will be set in the UART event register.)
This status bit indicates that the CTS signal was negated during transmission of this char-
acter. If this occurs, the CTS bit in the UART event register will also be set. This bit oper-
ates only if the CTS line is monitored by the SCC as determined by the DIAG bits.
14
—
REA
13
If the CTS signal was negated during transmission and the CP
transmits this character in the middle of buffer transmission, the
CTS signal could actually have been negated either during this
character’s transmission or during a buffer character’s transmis-
sion. In this case, the CP sets the CT bit both here and in the Tx
BD status word.
12
I
CT
11
Freescale Semiconductor, Inc.
For More Information On This Product,
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0
MC68360 USER’S MANUAL
Go to: www.freescale.com
9
0
NOTE
8
A
7
6
5
CHARSEND
4
3
2
1
0