MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 129

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

4.6.2 Bus Grant
The QUICC supports operand coherency; thus, if an operand transfer requires multiple bus
cycles, the QUICC does not release the bus until the entire transfer is complete. The asser-
tion of BG is therefore subject to the following constraints:
Externally, the BG signal can be routed through a daisy-chained network or a priority-
encoded network. The QUICC is not affected by the method of arbitration as long as the pro-
tocol is obeyed.
4.6.3 Bus Grant Acknowledge
An external device cannot request and be granted the external bus while another device is
the active bus master. A device that asserts BGACK remains the bus master until it negates
BGACK. BGACK should not be negated until all required bus cycles are completed. Bus
mastership is terminated at the negation of BGACK. When no other device requests the bus
after BGACK is negated, the QUICC will regain bus mastership.
The minimum time for the first bus cycle after BGACK negation depends on internal syn-
chronization and internal bus arbitration. This timing is therefore subject to the following con-
straints:
• The minimum time for BG assertion after BR is asserted depends on internal synchro-
• When working in synchronous mode (ASTM bit in the MCR is set), the minimum time
• During an external operand transfer, the QUICC does not assert BG until after the last
• During an external operand transfer, the QUICC does not assert BG as long as RMC is
• If the show cycle bits SHEN1–SHEN0 = 1x and if one of the QUICC internal masters is
• If SHEN1–SHEN0 = 00 and if one of the QUICC internal masters is making internal ac-
• If SHEN1–SHEN0 = 01, the QUICC does not assert BG to an external master.
• When working in synchronous mode (ASTM bit in the MCR is set) and SHEN0–SHEN1
• When working in asynchronous mode (ASTM bit in the MCR is cleared) and SHEN0–1
• If SHEN1–SHEN0 = 1 , another clock is added for internal bus arbitration.
nization.
can be one clock.
cycle of the transfer (determined by SIZx and DSACKx).
asserted.
making internal accesses, the QUICC does not assert BG until the transfer is terminat-
ed.
cesses, the external bus is granted away, and the QUICC continues to execute internal
bus cycles. In this case, the arbitration overhead (external bus idle time) is minimal.
= 00 and one of the QUICC internal masters requests an external accesses, the mini-
mum time can be one clock.
= 00 and one of the QUICC internal masters requests an external accesses, the mini-
mum time depends on internal synchronization plus one clock.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Bus Operation