MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 108

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
When the CPU32+ acknowledges hardware breakpoint (BKPT pin assertion or internal
breakpoint logic) with background mode disabled, the CPU32+ performs a word read from
CPU space, type 0, at an address corresponding to all ones on A4–A2 (BKPT#7), and the
T-bit (A1) is set. If this bus cycle is terminated by BERR, the QUICC performs hardware
breakpoint exception processing. If this bus cycle is terminated by DSACKx, the QUICC
ignores data on the data bus and continues execution of the next instruction.
The breakpoint operation flowchart is shown in Figure 4-23. Figure 4-24 and Figure 4-25
show the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes
supplied on the cycle and with an exception signaled, respectively.
4-32
The BKPT pin is sampled on the same clock phase as data and
is latched with data as it enters the CPU32+ pipeline. If BKPT is
asserted for only one bus cycle and a pipeline flush occurs be-
fore BKPT is detected by the CPU32+, BKPT is ignored. To en-
sure detection of BKPT by the CPU32+, BKPT can be asserted
until a breakpoint acknowledge cycle is recognized.
When the QUICC is configured for a 32-bit bus, the CPU32+ can
fetch two instructions simultaneously. Since there is only one
BKPT pin, the external user cannot break individually on those
instructions, but rather must break on both, causing the BKPT
exception to be taken after the first instruction and before the
second instruction. The internal breakpoint logic, however, can
individually assert a breakpoint for either instruction. (See the
BKAR and BKCR discussion in Section 6 System Integration
Module (SIM60) for details).
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE